An overview of standard cell based digital VLSI designImplementation of the first generation AsAP processorZhiyi Yu and Tinoosh MohseninVCL LaboratoryUC DavisOutline Overview of standard cell-based design Overview of AsAP Implementation of the first generation AsAPStandard cell based IC vs. Custom design IC Standard cell based IC:  Design using standard cells  Standard cells come from library provider Many different choices for cell size, delay, leakage power Many EDA tools to automate this flow Shorter design time Custom design IC:  Design all by yourself Higher performanceStandard cell based VLSI design flow Front end System specification and architecture HDL coding & behavioral simulation Synthesis & gate level simulation Back end Placement and routing DRC (Design Rule Check), LVS (Layout vsSchematic) dynamic simulation and static analysisOutline Overview of standard cell-based design Overview of AsAP Implementation of the first generation AsAPAsAP (Asynchronous Array of Simple Processors) A processing chip containing multiple uniform simple processor elements Each processor has its local clock generator Each processor can communicate with its neighbor processors using dual-clock FIFOsDiagram of a 3x3 AsAPMore information: http://www.ece.ucdavis.edu/vcl/asap/ InstMemALUMACControlDataMemClockIn-FIFO0In-FIFO1OutputOutline Overview of standard cell-based design Overview of AsAP Implementation of the first generation AsAPSimple diagram of the front-end design flowSystem SpecificationRTL CodingSynthesisGate level codeINV (.in (a), .out (a_inv));AND (.in1 (a_inv), .in2 (b), .out (c));Ex: c = !a & bSimple diagram of the back-end design flowgate level Verilog from synthesisPlace &RouteFinal layout(go for fabrication)DRCGate level VerilogLVSTiming informationGate level dynamic and/or static analysisDesign rulecheckLayout vs.schematicBack-end design of AsAP Technology: TSMC 0.18 μm CMOS Standard cell library: Artisan Tools Synthesis: Synopsis Design compiler Placement & Route: Cadence Encounter DRC & LVS: Calibre Static timing analysis: PrimetimeFlow of placement and routing Import needed files Floorplan Placement & in-place optimization Clock tree generation RoutingImport needed files Gate level verilog (.v)  Geometry information (.lef) Timing information (.lib)INV (.in (a), .out (a_inv));AND (.in1 (a_inv), .in2 (b), .out (c));INV: 1um width AND: 2 um widthINV: 1ns delay; AND: 2 ns delayINVANDabCDelay (a->c): 1ns + 2ns = 3nsFloorplan Size of chip Location of Pins Location of main blocks Power supply: give enough power for each gateVDD (Metal)Power supply (1.8V)currentGate 1 Gate 2 Gate 3 Gate 41.75vVoltage drop equation: V2 = V1 – I * R1.7v(need another power)1.65vVSSFloorplan of a single processorInst MemClockInFIFO0Data MemALUMACControlInFIFO0Placement & in-placement optimization Placement: place the gates In-placement optimization Why: timing information difference between synthesis and layout (wire delay) How: change gate size, insert buffers Should not change the circuit function!!Placement of a single processorClock tree Main parameters: skew, delay, transition timeClock tree of single processorRouting Connect the gates using wires Two steps Connect the global signals (power) Connect other signalsMetal Layer TopologyRoutingLayout of a single processorArea: 0.8mm x 0.8mmEstimated speed:450 MHzLayout of the first generation 6x6 AsAPOne processorArea: 30 mm^2in 180 nm CMOS36 processors114 PADsVerification after layout DRC (design rule check) LVS (layout vs. schematic) .GDS vs. (verilog + spice module) Gate level verilog dynamic simulation Mainly check the function  Different with synthesis resultUseful tools Dynamic Simulation:  Modelsim (Mentor), NC-verilog (Cadence), Active-HDL Synthesis:  Design-compiler, design-analyzer (Synopsys) Placement & Routing Encounter & icfb (Cadence) Astro (Synopsys) DRC & LVS Calibre (Mentor) Dracula (Cadence) Static Analysis Primetime