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UCD EEC 116 - EEC 116- Course Overview

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EEC 116 Lecture #1: Course OverviewPermissions to Use Conditions & AcknowledgmentOutlinePersonnelCourse MaterialsGradingWeightingColored PencilsLabs and CAD Software UsageMoore’s LawAdvances in Memory DensityHybrid to Monolithic TrendEducation Demand for Circuit DesignEducation Demand for System DesignProductivity TrendsWhat are the issues facing the industry ?Why worry about power? Power DissipationWhy worry about power? Chip Power DensityChip Power Density DistributionRecent Battery Scaling and Future TrendsWhy worry about power? Standby Power Chip Design StylesLogic Design FamiliesLogic Design FamiliesDesign ParametersCurrent State of the ArtHow Large Are Transistors?The First TransistorThe First Integrated CircuitAn Early “Planar” IC Intel 4004 Micro-ProcessorIntel Pentium 4 MicroprocessorIntel Westmere 6-Core MicroprocessorExpectationsMOS Transistor TypesMOS Transistor SymbolsNote on MOS Transistor SymbolsMOS Transistor StructureMOS Transistor Regions of OperationMOSFET Drain Current OverviewLogic Gate ExamplesFabrication ProcessSilicon Substrate ManufacturingSiliconA Silicon WaferA State-of-the-art WaferBuilding a Golf Course with Similar ProcessFabrication: Patterning of SiO2 Step IFabrication: Patterning of SiO2 Step IINMOS Transistor FabricationNMOS Transistor FabricationNMOS Transistor FabricationInverter Fabrication: LayoutInverter Fabrication: NWELL and OxidesInverter Fabrication: PolysiliconInverter Fabrication: DiffusionsInverter FabricationInverter FabricationNWELL MOS ProcessMore Complex ProcessesSilicon-On-Insulator (SOI) ProcessWiresChip WiresMemory ArrayMemory ArrayMemory ArrayTransistor LayoutAND Gate LayoutOR Gate LayoutFull Adder Layout16-bit Adder Layout16-bit Multiplier LayoutNext Topic: MOSFETs and Inverters MOSFET Drain Current OverviewA Fourth Region: SubthresholdNMOS Transistor I-V Characteristics INMOS Transistor I-V Characteristics IIMOS Transistor Operation: CutoffMOS Transistor Operation: InversionThreshold Voltage ComponentsThreshold Voltage SummaryThreshold Voltage (NMOS vs. PMOS)Body EffectHistorical BackgroundMemory, Processors and GraphicsMemory, Processors and GraphicsChip WiresEEC 116 Lecture #1:Course OverviewRajeevan Amirtharajah Bevan BaasUniversity of California, DavisJeff ParkhurstIntel CorporationAmirtharajah, EEC 116 Fall 2011 2Permissions to Use Conditions & Acknowledgment• Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al."This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. • Slides 13-17 Adapted from CSE477 VLSI Digital Circuits Lecture Slides by Vijay Narayanan and Mary Jane Irwin, Penn State UniversityAmirtharajah, EEC 116 Fall 2011 3Outline• Administrative Details• Survey of Digital IC Technology• MOS Fabrication• Layout Overview• MOSFET OverviewAmirtharajah, EEC 116 Fall 2011 4Personnel• Prof. Raj Amirtharajah (Instructor)Office: 3173 Kemper HallEmail: [email protected] put EEC 116 in email subject line.Office Hours: F 2 - 3 PM or by appointment.• Stanley HsuEmail: [email protected] Hours: Tu 2-4 2107 Kemper• LabsWednesdays 6 PM – 9 PM 2107 KemperAmirtharajah, EEC 116 Fall 2011 5Course Materials• TextbookDigital Integrated Circuits (2nded.) by J. Rabaey, A. Chandrakasan, and B. Nikolic• Suggested ReferencesCMOS Digital Integrated Circuits (3rded.) Kang and LeblebiciCMOS VLSI Design (4thed.) Weste, Harris (or earlier editions)• HandoutsLabs, lab report cover sheets, slides, and lecture notes available on course web page in PDF format.• Web Pagehttp://www.ece.ucdavis.edu/~ramirtha/EEC116/F11/F11.htmlLinked from SmartSiteAmirtharajah, EEC 116 Fall 2011 6Grading• Letter• A: 100 - 90%• B: 90 - 80%• C: 80 - 70%• D: 70 - 60%• F: below 60%• Expect class average to be around B- / C+• Curving will only help youAmirtharajah, EEC 116 Fall 2011 7Weighting• Labs 35%• Weekly Homework 5%Scale for each problem: 0 = poor effort, 1 = close, but fundamental problem, 2 = correct• Quizzes 10%Four throughout the quarter (approx. every other week), lowest score dropped (April 11, April 25, May 18, May 25)• Midterm 20%Monday, October 31, in class• Final 30%Wednesday, December 7, 1:00 - 3:00 PMCumulative, but emphasizes material after midtermAmirtharajah, EEC 116 Fall 2011 8Colored Pencils• Buy colored pencils or pens whose colors match Cadence layout tool layer colors– green– brown (orange next closest?)–red–blue– purple• Used for “stick diagrams”• Slightly transparent pencils or pens work bestAmirtharajah, EEC 116 Fall 2011 9Labs and CAD Software Usage• Need to know/learn Cadence/Spectre – Circuit Simulation• Can work on labs remotely using VNC, etc.Amirtharajah, EEC 116 Fall 2011 10Moore’s LawAmirtharajah, EEC 116 Fall 2011 11Advances in Memory DensitySource: Digital Integrated Circuits, 2nd ©Amirtharajah, EEC 116 Fall 2011 12Hybrid to Monolithic Trend• We continue to integrate multiple functions on a single chip– Mixture of Analog, Radio Frequency (RF), Digital– Graphics/Motherboard chipset an example of this• Cost and Performance driving market– Higher performance achieved on chip than off chip– Lower cost due to a single die versus multi-chip design– Saves on packaging, total area by eliminating redundant functions• System-on-a-Chip (SOC) conceptAmirtharajah, EEC 116 Fall 2011 13Education Demand for Circuit Design• Industry needs circuit designers– Not just logic designers• Must understand operation at transistor level– Not just digital designers• Must understand analog effects– Not just analog designers• Must be able to comprehend Deep Sub-Micron (DSM) effects (<0.13um)• Fundamental circuit knowledge critical– Similar techniques for bipolar transistors, NMOS (even relays and vacuum tubes!)– Must be able to exploit nanoscale devices in futureAmirtharajah, EEC 116 Fall 2011 14Education Demand for System Design• Industry needs system designers– Need to understand system implications of your design• Power Delivery, Clock Loading – What do you need– Need to design


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