GCD VLSI s Hello World CS250 Laboratory 1 Version 083010a August 30 2010 Yunsup Lee For the first lab assignment you will write an RTL model of a greatest common divisor GCD circuit and push it through all the VLSI tools you will use in the class The deliverables for this lab are a your working Verilog RTL checked into a revision control system called Subversion SVN b build results and reports generated by VCS DC Compiler Formality IC Compiler PrimeTime PX checked into SVN and c written answers to the questions given at the end of this document The lab assignment is due at the start of class on Monday September 13 You must submit your written answers electronically by adding a directory titled writeup to your lab project directory lab1 trunk writeup Electronic submissions must be in plain text or PDF format You are encouraged to discuss your design with others in the class but you must turn in your own work For this assignment you will become familiar with the VLSI tools you will use this semester learn how a design flows through the toolflow and practice Verilog coding Figure 1 shows the toolflow you will be using for the first lab You will use Synopsys VCS vcs to simulate and debug your RTL design After you get your design right you will use Synopsys Design Compiler dc shell xg t to synthesize the design Synthesis is the process of transforming an RTL model into a gate level netlist You will use Synopsys Formality fm shell to formally verify that the RTL model and the gate level model match VCS is used again to simulate the synthesized gate level netlist After obtaining a working gate level netlist you will use Synopsys IC Compiler icc shell to place and route the design Placement is the process by which each standard cell is positioned on the chip while routing involves wiring the cells together using various metal layers The tools will provide feedback on the performance and area of your design after both synthesis and place and route The results from place and route are more realistic but require much more time to generate After place and route you will generate and simulate the final gate level netlist using VCS Finally you will use this gate level simulation as a final test for correctness and to generate transition counts for every net in the design Synopsys PrimeTime PX pt shell takes these transition counts as input and correlate them with the capacitance values in the final layout to produce estimated power measurements Each piece of the toolflow has its own build directory and its own makefile Please consult the following tutorials for more information on using the various parts of the toolflow Tutorial Tutorial Tutorial Tutorial Tutorial 2 4 5 6 7 Bits and Pieces of CS250 s Toolflow Simulating Verilog RTL using Synopsys VCS RTL to Gates Synthesis using Synopsys Design Compiler Automatic Placement and Routing using Synopsys IC Compiler Power Analysis using Synopsys PrimeTime PX CS250 Lab Assignment 1 Version 083010a Fall 2010 Verilog Source Behav Verilog Source RTL VCS VCS Behav Sim RTL Sim Execute SIM Execute SIM 2 Std Cell Library Constraints Design Compiler Gate Level Netlist Guidance File Delay File Constraints Timing File Area Formality VPD Test Outputs DVE GUI VPD Test Outputs IC Compiler DP TLU Files Verification Results Floor Plan Design Vision GUI DVE GUI IC Compiler P R VCS Post Syn Sim Gate Level Netlist Delay File Constraints Timing File Area Layout Parasitics File Execute SIM VCS VPD Test Outputs IC Compiler GUI Post P R Sim DVE GUI Execute SIM VPD DVE GUI Test Outputs VPD2VCD VCD PrimeTime Power Estimates Figure 1 CS250 Toolflow for Lab 1 CS250 Lab Assignment 1 Version 083010a Fall 2010 3 Block Diagram and Module Interface The block diagram is shown in Figure 2 Your module should be named as gcdGCDUnit and must have the interface shown in Figure 3 We have provided you with a test harness that will drive the inputs and check the outputs of your design gcdTestHarness operands bits A gcdGCDUnit operands bits B operands val operands rdy result bits data result val clk result rdy reset Figure 2 Block diagram for GCD Test Harness module gcdGCDUnit parameter W 16 input clk reset input W 1 0 operands bits A input W 1 0 operands bits B input operands val output operands rdy Operand A Operand B Are operands valid ready to take operands output W 1 0 result bits data output result val input result rdy GCD Is the result valid ready to take the result Figure 3 Interface for the GCD module CS250 Lab Assignment 1 Version 083010a Fall 2010 4 Getting Started You can follow along through the lab yourself by typing in the commands marked with a symbol at the shell prompt To cut and paste commands from this lab into your bash shell and make sure bash ignores the character just use an alias to undefine the character like this alias All of the CS250 laboratory assignments should be completed on an EECS Instructional machine Please see the course website for more information on the computing resources available for CS250 students Once you have logged into an EECS Instructional you will need to setup the CS250 toolflow with the following commands source cs250 tools cs250 bashrc You will be using SVN to manage your CS250 laboratory assignments Please see Tutorial 1 Using SVN to Manage Source RTL for more information on how to use SVN Every student has their own directory in the repository which is not accessible to other students Assuming your username is yunsup you can checkout your personal SVN directory using the following command svn checkout SVNREPO yunsup vc To begin the lab you will need to make use of the lab harness located in cs250 lab1 The lab harness provides makefiles scripts and the Verilog test harness required to complete the lab The following commands copy the lab harness into your SVN directory and adds the new project to SVN To simplify the rest of the lab we will also define a LABROOT environment variable which contains the absolute path to the project s top level root directory cd vc mkdir lab1 svn add lab1 cd lab1 mkdir trunk branches tags cd trunk cp R cs250 lab1 v gcd cd svn add svn commit m Initial checkin svn update cd trunk LABROOT PWD The resulting LABROOT directory contains the following primary subdirectories src contains your source Verilog build contains automated makefiles and scripts for building your design and build manual is the directory to tryout the VLSI tools manually The src directory contains the Verilog test harness and other Verilog