EECS130 Integrated Circuit DevicesSlide Number 2TerminologyFoundry (Fab)Cleanroom StandardsSlide Number 6 Oxidation of SiliconSlide Number 8Slide Number 9Slide Number 10Slide Number 11Other Advanced Lithography MethodsSlide Number 13Slide Number 14Slide Number 15Slide Number 16Slide Number 17Slide Number 18Slide Number 19Slide Number 20Slide Number 21Slide Number 22Slide Number 23Slide Number 24Slide Number 25Slide Number 26Slide Number 27Slide Number 28Slide Number 29Slide Number 30Slide Number 31Slide Number 32Slide Number 33EECS130 Integrated Circuit DevicesProfessor Ali Javey9/13/2007Fabrication TechnologyLecture 1Silicon Device Fabrication TechnologyOver 1015 transistors (or 100,000 for every person in the world) are manufactured every year. Variations of this versatile technology are used for flat-panel displays, micro-electro-mechanical systems (MEMS), and even DNA chips for DNA screening...TerminologySSI (Small Scale Integration) – few transistorsMSI (Medium Scale Integration) – hundredsLSI (Large Scale Integration) - thousandsVLSI (Very Large Scale Integration) - millionsULSI (Ultra Large Scale Integration)Foundry (Fab)• Foundry (also called a fab for fabrication plant) is used to refer to a factory where devices like integrated circuits are manufactured. The central part of a fab is a cleanroom.• Note the difference between a fab and a lab.Cleanroom StandardsFederal Standard Class LimitsCLASSMEASURED PARTICLE SIZE (MICROMETERS)0.1 0.2 0.3 0.5 5.01 35 7.5 3 1 NA10 350 75 30 10 NA100 NA 750 300 100 NA1,000 NA NA NA 1,000 710,000 NA NA NA 10,000 70100,000 NA NA NA 100,000 700Why do we need cleanrooms?Introduction to Device FabricationOxidationLithography &Etching Ion ImplantationAnnealing & DiffusionThin Film DepositionOxidation of SiliconSi + O2 → SiO2 Si +2H2 O → SiO2 + 2H2Dry Oxidation :Wet Oxidation :Thin oxideThick oxideSi Wafers O2 N2H2O or TCE(trichloroethylene)Quartz tube Resistance-heated furnaceFlowcontrollerOxidation of SiliconEXAMPLE : Sequential Oxidation(a) How long does it take to grow 0.1μm of dry oxide at 1000 oC ? (b) After step (a), how long will it take to grow an additional 0.2μm of oxide at 900 oC in a wet ambient ?Solution: (a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to grow 0.1μm of oxide.(b) Use the “900oC wet” curve only. It would have taken 0.7hr to grow the 0.1 μm oxide and 2.4hr to grow 0.3 μm oxide from bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.Oxidation of SiliconLithographyResist CoatingExposureDevelopmentEtching and Resist StripPhotoresistOxideSi(a)OpticalLens systemDeep Ultraviolet LightPhotomask withopaque and clear patternsSi SiSiSiPositive resist Negative resist(c)(d)(b)LithographyPhotolithography Resolution Limit, R• R ≥ kλdue to optical diffraction• Wavelength λneeds to be minimized. (248 nm, 193 nm, 157 nm?)• k (∼ 0.5) can be reduced by• Large aperture, high quality lens• Small field, step-and-repeat using stepper• Phase-shift mask• Optical proximity correction• Lithography is difficult and expensive. There are ~20 lithography steps in an IC process.Other Advanced Lithography Methods• EUV Photolithography• E-beam Lithography• Dip-pen lithographyDip-pen Lithography, Chad Mirkin, NWURichard FeynmanPattern Transfer–EtchingIsotropic etching Anisotropic etchingSiO2SiO2SiO2 (1) (2)(3)photoresistphotoresistSiO2 (1) (2) photoresistphotoresistSiO2SiO2(3)wet etch dry etchPattern Transfer–EtchingDry Etching (also known as Plasma Etching, or Reactive-Ion Etching) is anisotropic.• Silicon and its compounds can be etched by plasmas containing F.• Aluminum can be etched by Cl.• Some concerns :- Selectivity and End-Point Detection- Plasma Process-Induced Damage or Wafer Charging Damage and Antenna EffectScanning electron microscope view of a plasma-etched (dry-etched) 0.16 μm pattern in polycrystalline silicon film.DopingIon ImplantationSi IonsMasking materialfor example resist or SiO2• The dominant doping method• Excellent control of dose (cm-2)• Good control of implant depth with energy (KeV to MeV)• Repairing crystal damage and dopant activation requires annealing, which can cause dopant diffusion and loss of depth control.Ion implantationPhosphorous Density Profile after ImplantationDopingOther Doping Methods• Gas-Phase Doping : Used to dope Si with P usingPOCl3 .• Solid-Source Doping : Dopant diffuses from a doped solid film (SiGe or oxide) into Si.• In-Situ Doping : Used to dope deposited films during film deposition.Dopant DiffusionDtxoeDtNtxN4/2),(−⋅=πN : Nd or Na (cm-3)No : dopant atoms per cm2t : diffusion timeD : diffusivity, is the approximate distance of dopant diffusionp-type SiSiO2 n-type diffusion layerJunction depth, xjDtDopant DiffusionSome applications need very deep junctions (high T, long t). Others need very shallow junctions (low T, short t).D increases with increasing temperature.Dopant DiffusionShallow Junction and Rapid Thermal Annealing• After ion implantation, thermal annealing is required. Furnace annealing causes too much diffusion of dopant for some applications.• In rapid thermal annealing (RTA), the wafer is heated to high temperature in seconds by a bank of heat lamps.Also RTO (oxidation), RTCVD (chemical vapor deposition), RTP (processing).Thin-Film DepositionThree Kinds of SolidCrystalline PolycrystallineSilicon wafer Thin film of Si or metal. Thin film of SiO2 or Si3 N4 .AmorphousThin-Film Deposition• Metal layers for device interconnect• Inter-metal dielectric• Poly-Si for transistor gate• Barrier against interdiffusion• EncapsulationSputtering Target materialdeposited on waferSi Wafer Ion (Ar+) Sputtering targetAtoms sputtered out of the targetSchematic Illustration of Sputtering ProcessChemical Vapor Deposition (CVD) Molecules of deposited
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