EECS130 Integrated Circuit DevicesAnnouncementsSlide Number 3Vt Roll-offWhy Does Vt Decrease with L?― Potential Barrier ConceptEnergy-Band Diagram from Source to DrainHow to Reduce WdepReducing the Gate Insulator Thickness and ToxeTunneling Leakage CurrentReplacing SiO2 with HfO2---High-k DielectricChallenges of High-K TechnologyMore Scalable Device StructuresUltra-Thin-Body (UTB) MOSFET New Structure I--Ultra-Thin-Body MOSFET Preparation of Silicon-on-Insulator (SOI) Substrate Cross-Section of SOI Circuits New Struture II--Multi-Gate MOSFET and FinFET FinFET FinFET Process Flow Variations of FinFET Tall FinFET with Lg=10nm Nanowire FinFET Device Simulation and Process Simulation Example of Device Simulation--- Density of Inversion Charge in the Cross-Section of a FinFET Body Example of Process SimulationEECS130 Integrated Circuit DevicesProfessor Ali Javey11/01/2007MOSFETs– Lecture 5Announcements•HW7 set is due now•HW8 is assigned, but will not be collected/graded.MOSFET Technology Scaling Technology Scaling ―Small is Beautiful• New technology node every three years or so. Defined by minimum metal line width.• All feature sizes, e.g. gate length, are ~70% of previous node.YEAR 1992 1995 1997 1999 2001 2004 2007 2010Technology Generation0.5μm0.35μm0.25μm0.18μm0.13μm90nm65nm45nmVt Roll-off65nm technology. EOT=1.2nm, Vdd =1VK. Goto et al., (Fujitsu) IEDM 2003• Vt roll-off: Vt decreases with decreasing Lg .• It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small.Why Does Vt Decrease with L?―Potential Barrier Concept• When L is small, smaller Vg is needed to reduce the barrier to 0.2V, i.e. Vt is smaller.• Vt roll-off is greater for shorter L~0.2VVdsEcVgs =0VVgs =Vt-longVgs =0VVgs =Vt-shortLong ChannelShort ChannelN+ SourceN+ DrainVg =0VVg =Vt• Vds dependenceEnergy-Band Diagram from Source to Drain• L dependencelong channelVdsshort channelsource/channel barrierlong channelshort channelVgslog(Ids )VdsVds =0Vds =VddVds =VddHow to Reduce WdepdepoxBsBfboxBsbodyBfbtWCVCqNVVφεφφεφ222222 ++=++=– If Nbody is increased, Cox should be increased in order to keep Vt the same.– Wdep can be reduced in proportion to Tox .• Wdep can be reduced by increasing NbodyReducing the Gate Insulator Thickness and Toxe• Oxide thickness has been reduced over the years from 300nm to 1.2nm.• Why reduce oxide thickness?– Larger Cox to raise Ion– Reduce subthreshold swing– Control Vt roll-off• Thinner is better. However, if the oxide is too thin– Breakdown due to high electric field– Leakage currentTunneling Leakage Current• For SiO2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor. • HfO2 has several orders lower leakage for the same EOT.Replacing SiO2 with HfO2 ---High-k Dielectric• HfO2 has a relative dielectric constant (k) of ~24, six times large than that of SiO2 . • For the same EOT, the HfO2 film presents a much thicker (albeit a lower) tunneling barrier to the electrons and holes. • Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.(After W. Tsai et al., IEDM’03)Challenges of High-K Technology• The challenges of high-k dielectrics are – chemical reactions between them and the silicon substrate and gate,– lower surface mobility than the Si/SiO2 system– too low a Vt for P-channel MOSFET (as if there is positive charge in the high-k dielectric).• A thin SiO2 interfacial layer may be inserted between Si-substrate and high-k film.More Scalable Device Structures• Vertical Scaling is important. For example, reducing Tox gives the gate excellent control of Si surface potential. • But, the drain could still have more control than the gate along another leakage current path that is some distance below the Si surface. (Right figure.)CdCgleakage pathDSCdN+P-SubCgToxVgsVdsUltra-Thin-Body (UTB) MOSFET• MOSFET built on very thin silicon film on an insulator (SiO2 ).• Since the silicon film is very thin, perhaps less than 10nm, no leakage path is very far from the gate.Source DrainTSi = 3 nmGateSiO2SiElectron Micrograph of UTB MOSFET GateN+N+SiO2New Structure I--Ultra-Thin-Body MOSFET• The subthreshold leakage is reduced as the silicon film is made thinner. Tox =1.5nm, Nsub =1e15cm-3, Vdd =1V, Vgs =0Preparation of Silicon-on-Insulator (SOI) Substrate• Initial Silicon wafer A and B• Oxidize wafer A to grow SiO2• Implant hydrogen into wafer A• Place wafer A, upside down, over wafer B. • A low temperature annealing causes the two wafers to fuse together.• Apply another annealing step to for H2 bubbles and split wafer A.• Polish the surface and the SOI wafer is ready for use. • Wafer A can be reused.Cross-Section of SOI Circuits• Due to the high cost of SOI wafers, only some microprocessors, which command high prices and compete on speed, have embraced this technology.• In order to benefit from the UTB concept, Si film thickness must be agreesively reduced to ~ Lg/4SiBuried OxideNew Struture II--Multi-Gate MOSFET and FinFET• The second way of eliminating deep leakage paths is to provide gate control from more than one side of the channel.• The Si film is very thin so that no leakage path is far from one of the gates. • Because there are more than one gates, the structure may be called multi-gate MOSFET. Source DrainGate 1Gate 1VgToxTSiSiGate 2Gate 2double-gate MOSFETFinFET• One multi-gate structure, called FinFET, is particularly attractive for its simplicity of fabrication.• Called FinFET because its silicon body resembles the back fin of a fish. • The channel consists of the two vertical surfaces and the top surface of the fin. Question: What is the channel width, W?Answer: The sum of twice the fin height and the width of the fin.SourceSourceDrainGateLgFinFET Process Flow Poly Gate Deposition/LithoGate EtchSpacer FormationS/D Implant + RTASilicidationSOI SubstrateFin PatterningSi FinBOXPolyResistSi3 N4SpacerNiSiVariations of FinFETNanowire FinFETShort FinFETSDGBuried OxideSDGTsiLgSGDTall FinFET• Tall FinFET has the advantage of providing a large W and therefore large Ion while occupying a small footprint. • Short FinFET has the advantage of less challenging lithography and etching. • Nanowire FinFET gives the gate even more control over the silicon wire by surrounding it.Tall
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