Lecture #35Bias-Temperature Stress MeasurementClarification: Effect of Interface TrapsInvention of the Field-Effect TransistorModern Field Effect Transistor (FET)The Bulk-Si MOSFETN-channel vs. P-channelEnhancement Mode vs. Depletion ModeCMOS Devices and Circuits“Pull-Down” and “Pull-Up” DevicesCMOS NAND GateCMOS NOR GateCMOS Pass GateEE130 Lecture 35, Slide 1Spring 2007Lecture #35OUTLINE The MOS Capacitor: Final commentsThe MOSFET: •Structure and operationReading: Chapter 17.1EE130 Lecture 35, Slide 2Spring 2007Bias-Temperature Stress MeasurementFBoxMVCQ Na+ located at upper SiO2 interface no effect on VFBNa+ located at lower SiO2 interface reduces VFBVFBoxSITxoxSiOoxFMSFBCQdxxxCQVo)()(102Used to determine mobile charge density in MOS dielectric (units: C/cm2)Positive oxide charge shifts the flatband voltage in the negative direction:EE130 Lecture 35, Slide 3Spring 2007Clarification: Effect of Interface TrapsTraps cause “sloppy” C-V and also greatly degrade mobility in channeloxSITGCQV)(“Donor-like” traps arecharge-neutral whenfilled, positively chargedwhen emptyPositive oxide chargecauses C-V curve toshift toward left (more shift as VG decreases)(a)(a) (b)(b)(c)(c)EE130 Lecture 35, Slide 4Spring 2007In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955.Invention of the Field-Effect TransistorEE130 Lecture 35, Slide 5Spring 2007Modern Field Effect Transistor (FET)•An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductorModulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrodeEE130 Lecture 35, Slide 6Spring 2007The Bulk-Si MOSFET•Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode SubstrateGateSource DrainMetal-Oxide-Semiconductor Field-Effect Transistor:GATE LENGTH, LgOXIDE THICKNESS, ToxJUNCTION DEPTH, XjM. Bohr, Intel DeveloperForum, September 2004Desired characteristics:• High ON current• Low OFF current•“N-channel” & “P-channel” MOSFETs operate in a complementary manner“CMOS” = Complementary MOS|GATE VOLTAGE|CURRENTVTEE130 Lecture 35, Slide 7Spring 2007N-channel vs. P-channel•For current to flow, VGS > VT•Enhancement mode: VT > 0•Depletion mode: VT < 0–Transistor is ON when VG=0VP-type SiN+ poly-Sin-type SiP+ poly-SiNMOS PMOSN+ N+ P+ P+•For current to flow, VGS < VT•Enhancement mode: VT < 0•Depletion mode: VT > 0–Transistor is ON when VG=0VEE130 Lecture 35, Slide 8Spring 2007Enhancement Mode vs. Depletion ModeEnhancement Mode Depletion ModeConduction between source and drain regions is enhanced by applying a gate voltageA gate voltage must be appliedto deplete the channel region in order to turn off the transistorEE130 Lecture 35, Slide 9Spring 2007CMOS Devices and CircuitsCIRCUIT SYMBOLSN-channelMOSFETP-channelMOSFETGNDVDDSSDDCMOS INVERTER CIRCUITVINVOUTVOUTVIN0VDDVDDINVERTERLOGIC SYMBOL• When VG = VDD , the NMOSFET is on and the PMOSFET is off. • When VG = 0, the PMOSFET is on and the NMOSFET is off.EE130 Lecture 35, Slide 10Spring 2007“Pull-Down” and “Pull-Up” Devices•In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD.–An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD)–A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND)F(A1, A2, …, AN)PMOSFETs onlyNMOSFETs only……Pull-upnetworkPull-downnetworkVDDA1A2ANA1A2ANinput signalsEE130 Lecture 35, Slide 11Spring 2007CMOS NAND GateA B F0 0 10 1 11 0 11 1 0AFBA BVDDEE130 Lecture 35, Slide 12Spring 2007CMOS NOR GateAFBABVDDA B F0 0 10 1 01 0 01 1 0EE130 Lecture 35, Slide 13Spring 2007CMOS Pass GateAXYAY = X if
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