Lecture #42Integrated Circuit TechnologyFormation of Insulating FilmsPatterning the LayersPattern Transfer by EtchingThe Photo-Lithographic ProcessAdding Dopants into SiN-channel MOSFETCMOS TechnologySlide 10Modern CMOS Fabrication ProcessSlide 12Slide 13Intel’s 65 nm CMOS TechnologyCMOS InverterCMOS LatchupHow to Prevent CMOS LatchupIC Technology TrendsEE130 Lecture 42, Slide 1 Spring 2007Lecture #42OUTLINE •IC technology•MOSFET fabrication process•CMOS latch-upReading: Chapter 4Die photo of Intel Penryn processor(Intel®CoreTM2 family) courtesy of ChipworksCross-sectional SEM view ofAMD Athlon 64 x2 processorEE130 Lecture 42, Slide 2 Spring 2007“Planar” fabrication process:Simultaneous fabrication of many “chips” on a wafer, each comprising an integrated circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistorsMethod:Sequentially lay down and pattern thin films of semiconductors, metals and insulators.Materials used in a basic CMOS integrated circuit:• Si substrate – selectively doped in various regions• SiO2 insulator• Polycrystalline silicon – used for the gate electrodes• Metal contacts and wiring300mm Si waferIntegrated Circuit TechnologyEE130 Lecture 42, Slide 3 Spring 2007Formation of Insulating Films•The favored insulator is pure silicon dioxide (SiO2).•A SiO2 film can be formed by one of two methods:1. Oxidation of Si at high temperature in O2 or steam ambient2. Deposition of a silicon dioxide filmASM A412batchoxidationfurnaceApplied Materials low-pressure chemical-vapor deposition (CVD) chamberEE130 Lecture 42, Slide 4 Spring 2007Patterning the LayersLithography refers to the process of transferring a pattern to the surface of the waferEquipment, materials, and processes needed:•A mask (for each layer to be patterned) with the desired pattern•A light-sensitive material (called photoresist) covering the wafer so as to receive the pattern•A light source and method of projecting the image of the mask onto the photoresist (“printer” or “projection stepper” or “projection scanner”)•A method of “developing” the photoresist, that is selectively removing it from the regions where it was exposedPlanar processing consists of a sequence of additive and subtractive steps with lateral patterningoxidationdepositionion implantationetching lithographyEE130 Lecture 42, Slide 5 Spring 2007In order to transfer the photoresist pattern to an underlying film, we need a “subtractive” process that removes the film, ideally with minimal change in the pattern and with minimal removal of the underlying material(s) Selective etch processes (using plasma or aqueous chemistry) have been developed for most IC materialsJargon for this entire sequence of process steps: “pattern using XX mask”photoresistSiO 2First: pattern photoresistSiWe have exposed mask pattern, and developed the resistetch stops on silicon (“selective etchant”)oxide etchant … photoresist is resistant.Next: Etch oxideonly resist is attackedLast: strip resistPattern Transfer by EtchingEE130 Lecture 42, Slide 6 Spring 2007Oxidation or thin-film depositionopticalmaskoptionaladditionalprocessstep(s)photoresist coatingphotoresistremoval (ashing)spin, rinse, dryetchphotoresistexposureThe Photo-Lithographic ProcessphotoresistdevelopEE130 Lecture 42, Slide 7 Spring 2007Suppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an “ion gun” called an ion implanter, into the surface of the wafer. Typical implant energies are in the range 1-200 keV. After the ion implantation, the wafers are heated to a high temperature (>1000oC). This “annealing” step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites.Adding Dopants into SiEaton HE3High-Energy Implanter,showing the ion beam hitting theend-stationEE130 Lecture 42, Slide 8 Spring 2007N-channel MOSFETSchematic Cross-Sectional ViewLayout (Top View)4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnectschannelwidth, Wgate length, LgEE130 Lecture 42, Slide 9 Spring 2007CMOS TechnologyBoth n-channel and p-channel MOSFETs arefabricated on the same chip (VTp = -VTn )•Primary advantage:–Lower average power dissipation•Ideally, in steady state either the NMOS or PMOS device is off, so there is no DC current path between VDD & GND•Disadvantages:–More complex (expensive) process –Latch-up problemEE130 Lecture 42, Slide 10 Spring 2007p-substrateNDn-wellNDn-wellNAp-wellSingle-well technology• n-well must be deep enough to avoid vertical punch-throughNeed p-regions (for NMOS) and n-regions (for PMOS)on the wafer surface, e.g.:NATwin-well technology• Wells must be deep enough to avoid vertical punch-throughp- or n-substrate(lightly doped)EE130 Lecture 42, Slide 11 Spring 2007Modern CMOS Fabrication Process•A series of lithography, etch, and fill steps are used to create silicon mesas isolated by silicon-dioxide•Lithography and implant steps are used to form the NMOS and PMOS wells and to set the channel doping levelsp-type Silicon Substratep-type Silicon SubstrateShallow Trench Isolation (STI) - oxidep-type Silicon SubstrateEE130 Lecture 42, Slide 12 Spring 2007•The thin gate dielectric layer is formed•Poly-Si is deposited and patterned to form gate electrodes•Lithography and implantation are used to form NLDD and PLDD regionsp-type Silicon Substratep-type Silicon Substratep-type Silicon SubstrateEE130 Lecture 42, Slide 13 Spring 2007•A series of steps is used to form the deep source / drain regions as well as body contacts•A series of steps is used to encapsulate the devices and form metal interconnections between them.p-type Silicon Substratep-type Silicon SubstrateEE130 Lecture 42, Slide 14 Spring 2007Intel’s 65 nm CMOS Technology• Lg = 35 nm• Tox = 1.2 nm• Strained Si channelNMOS: tensile capping layerPMOS: epitaxial Si1-xGex embedded in S/DNMOSFETPMOSFETEE130 Lecture 42, Slide 15 Spring 2007CMOS Invertern+p+p+n+n+p+n-wellp-SiVinVoutVDDVinVoutVDDEquivalent circuit:VSSSiO2EE130 Lecture 42, Slide 16 Spring 2007Coupled parasitic npn and pnp bipolar transistors:If either BJT enters the active mode, the SCR will enter into the forward conducting mode (large current flowing between VDD and GND) if npnpnp > 1=> circuit
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