1EE130 Lecture 29, Slide 1Spring 2003Lecture #29ANNOUNCEMENTS• HW#15 will be for extra credit• Quiz #6 (Thursday 5/8) will include MOSFET C-V• No late Projects will be accepted after Thursday 5/8• The last Coffee Hour will be held this Thursday at 5/8• Prof. King & TAs will hold office hours through 5/22OUTLINE• MOSFET scaling (reprise)• SOI technology• MOS memory devicesEE130 Lecture 29, Slide 2Spring 2003Moore’s Law1,00010,000100,0001,000,00010,000,000100,000,0001,000,000,0001970 1980 1990 2000 20104004808080868008Pentium® Processor486™ DX Processor386™ Processor286Pentium® II ProcessorPentium® III ProcessorPentium® 4 ProcessorHeading toward 1 billion transistors in 2007# transistors/chip doubles every 1.5 to 2 years2EE130 Lecture 29, Slide 3Spring 2003VDD=0.75V0.85VIntrinsic Gate Delay (CgateVDD/ IDsat)EE130 Lecture 29, Slide 4Spring 2003Silicon on Insulator (SOI) Technology• Transistors are fabricated in a thin single-crystal Si layer on top of an electrically insulating layer of SiO29 Simpler device isolation Æ savings in circuit layout area9 Low junction capacitances Æ faster circuit operation9 Better soft-error immunity9 No body effect8 Higher costTSOI3EE130 Lecture 29, Slide 5Spring 2003Partially Depleted SOI (PD-SOI)Floating body effect (history dependent):1. When a PD-SOI NMOSFET is in the ON state, at moderate-to-high VDS, holes are generated via impact ionization near the drain2. Holes are swept into the neutral body, collecting at the source junction3. The body-source pn junction is forward biased4. Æ VTis lowered Æ IDsatincreases Æ “kink” in output IDvs. VDScurvebodyBsdmdmSOIqNWWT)2(2 where, ψε=>EE130 Lecture 29, Slide 6Spring 2003Fully Depleted SOI (FD-SOI)• No floating body effect!• VTis sensitive to SOI film thickness• Poorer control of short-channel effects due to fringing electric field from drain• Elevated S/D contact structureneeded to reduce RS, RDbodyBsdmdmSOIqNWWT)2(2 where, ψε=<Silicon SubstrateSource DrainSiO2SOIGateGate4EE130 Lecture 29, Slide 7Spring 2003Semiconductor Memory• Volatile– Static random access memory (SRAM)– Dynamic random access memory (DRAM)• Non-Volatile– Mask programmed ROM– Programmable Read-Only Memory (PROM)– Electrically programmable ROM (EPROM)– Electrically erasable PROM (E2PROM)– Flash EPROMEE130 Lecture 29, Slide 8Spring 20036-Transistor CMOS SRAM CellWLBLVDDM5M6M4M1M2M3BLQQ~1 ns read time<10 ns write time5EE130 Lecture 29, Slide 9Spring 20036T-SRAM: Layout • Modern processes can fit a 6T SRAM cell in ~1.0µm2VDDGNDQQWLBLBLM1M3M4M2M5 M6EE130 Lecture 29, Slide 10Spring 2003• Low standby powerÆ low OFF current (e.g. 1 pA/cell)Æ large VTis required• Soft error immunitySRAM Scaling Challenges6EE130 Lecture 29, Slide 11Spring 20031-Transistor DRAM CellCSM1BLWLCBLWLXBLVDD−VTVDD/2VDDGNDWrite "1"Read "1"sensingVDD/2∆VVBLVPRE–VBITVPRE–()CSCSCBL+--- ------ ------ --- -- - ---==Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically around 250 mV.~10 ns read time~100 ns write timeEE130 Lecture 29, Slide 12Spring 2003DRAM Cell Structure• Desired characteristics:9 low power consumption 9 long retention time9 “fast” access time9 soft error immunity• ≥25fF/cell is required for sensing signal margin and retention timeCapacitorTransistorGateBodySourceDrain7EE130 Lecture 29, Slide 13Spring 2003Advanced DRAM Capacitor StructuresCell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench Capacitor Stacked CapacitorCapacitor dielectric layerCell plateWord lineInsulating LayerIsolationTransfer gateStorage electrodeEE130 Lecture 29, Slide 14Spring 2003• Long retention time Æ low OFF current (~1 fA)– large VTis requiredDRAM Scaling Challenge• Fast access time Æ high ON current (~100 µA)– large (VGS-VT) is required=> VDDcannot be scaled down aggressively, for low power consumption2233GateGate(WL)(WL)STISTICapacitorCapacitor1144Possible charge leakage paths shown here:8EE130 Lecture 29, Slide 15Spring 2003Tunnel OxideN+ DrainN+ SourceFloating gateInter-poly OxideControl GateSubstrate• Tunnel oxide: 8 nm thermal oxide• Floating gate: 100 nm N+ poly-Si• Inter-poly oxide: 16 nm CVD oxide orOxide/Nitride/Oxide stack• To program this device, electrons are injected from the channel inversion layer into the floating gate through the tunnel oxide.• The inter-poly oxide is thick, to prevent electrons from tunneling through it.Flash EPROM Cell StructureEE130 Lecture 29, Slide 16Spring 2003Program by Hot Electron InjectionSubstrateDrainSource+5V+10V0VAFG• Electrons are accelerated by the lateral E-field and gain enough kinetic energy at point A (near the drain) to surmount the potential barrier.• Because of the control-gate bias, electrons are injected into the floating gate.Floating gatechannel3.15eVTunneloxide9EE130 Lecture 29, Slide 17Spring 2003SubstrateDrainSource0V+18V0VAFG• For a sufficiently high control-gate bias, electrons can tunnel from the channel inversion layer into the floating gate.channel3.15eVFloating gateTunneloxideProgram by Fowler-Nordheim TunnelingEE130 Lecture 29, Slide 18Spring 2003SubstrateDrainSource0V-18V0VFloating gatechannel3.15eVTunneloxide• Under a large negative control-gate bias, electrons tunnel out of the floating gate into the substrate.Erase Operation10EE130 Lecture 29, Slide 19Spring 2003VR=3V(1) Programmed stateVT=VT2=5V, IDS=0VDS=2VSubstrateDrainSource0VVR=3VVDS=2VSubstrateDrainSource0V(2) Erased stateVT=VT1=1V, IDS=50 uAVCGIDSErased ProgrammedVT1VT2VR50uATwo VTstates:0ASensing the Stored DataEE130 Lecture 29, Slide 20Spring 2003Each memory cell can be addressed individually by its word line (gate) and bit line (drain)NOR Flash Memory Architecture11EE130 Lecture 29, Slide 21Spring 2003• For each bit line, 16 or 32 cells are connected, with one select transistor at each end of the bit line.• Programmed VT> 0 VErased VT< 0 V• The source/drain region between each two adjacent cells are shared Æ high densityNAND Flash Memory ArchitectureEE130 Lecture 29, Slide 22Spring 2003NORNANDChip Density Medium (64MB) Very high (2GB)Programming mechanismHot electron injection F-N tunnelingProgramming speed 1us ~10us 1msErasing speed ms byte/block erase ms block eraseRandom access Yes No Application Code storage Data storageVendor Intel, AMDSanDisk,
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