1EE130 Lecture 23, Slide 1Spring 2003Lecture #23ANNOUNCEMENTS• Quiz #5 will be given at the beginning of class on Thursday (4/17)– topics to be covered: BJT transient response, MOS band diagrams– closed book; 5 pages of notes + calculator allowedOUTLINE• MOS non-idealities (cont.)• VTadjustment• MOSFET structure and operationReading: Course Reader Chapter 3.1(Textbook Chapters 18.3, 17.1-2)EE130 Lecture 23, Slide 2Spring 2003• A heavily doped film of polycrystalline silicon (poly-Si) is typically employed as the gate-electrode material in modern MOS devices.– There are practical limits to the electrically active dopant concentration (usually less than 1x1020cm-3)⇒ The gate must be considered as a semiconductor, rather than a metalPoly-Si Gate Depletion P-type SiN+ poly-Sin-type SiP+ poly-SiNMOSPMOS2EE130 Lecture 23, Slide 3Spring 2003)(TpolyGoxinvVVVCQ −−=How can gate depletion be minimized?MOS Band Diagram with Gate DepletionVGis effectively reduced:EcEFSEvEvqVGqψBWdmP-type SiN+ poly-Si gateEcqVpolyWpolySi biased to inversion:polypolySipolyqNVWε2=EE130 Lecture 23, Slide 4Spring 2003N+ poly-SiGauss’s Law dictates polyoxoxpolyqNW /ε=)3/( 112211polyoxSiOSipolySiOoxpolyoxWtWtCCC+=+=+=−−εεεGate Depletion Effecttoxis effectively increased: )3/()(2polyoxSiOTGinvWtVVQ+⋅−=εp-type Si------+ + + + + +N++ +-- -CpolyCox3EE130 Lecture 23, Slide 5Spring 2003Example: GDEVox, the voltage across a 2 nm thin oxide, is 1 V. The n+poly-Si gate active dopant concentration Npolyis 8 ×1019cm-3and the Si substrate doping concentration NAis 1017cm-3. Find (a) Wpoly, (b) Vpoly, and (c) VG.Solution:(a)nm3.1cm108C106.1cm102V1)F/cm(1085.89.3//31919714=×⋅×⋅×⋅××===−−−−polyoxoxoxpolyoxoxpolyqNtVqNWεεEE130 Lecture 23, Slide 6Spring 2003(b)polypolySipolyqNVWε2=V 11.02/2==SipolypolypolyWqNVε(c)V 97.0V 11.0V 1V 84.0V 98.0V 98.0ln2 2=+++−=−=+−=+++=GiAGFBpolyoxBFBGVnNqkTqEVVVVVψIs the loss of 0.11V significant?4EE130 Lecture 23, Slide 7Spring 2003The average inversion-layer location below the Si/SiO2interface is called the inversion-layer thickness, Tinv.-50 -40 -30 -20 -10 0 10 20 30 40 50AElectron DensityQuantummechanical theorySiO2poly-Sidepl etionregiongate Physical Tox effective ToxÅInversion-Layer Thickness TinvEE130 Lecture 23, Slide 8Spring 200333invpolyoxoxeTWtT ++=at VG=Vdd(VG+ VT)/Toxcan be shown to be the average electric field in the inversion layer. Tinvof holes is larger than that of electrons because of the difference in effective masses.Electrical Oxide Thickness, Toxe5EE130 Lecture 23, Slide 9Spring 20033/3/invpolyoxoxeTWtT ++=)(TGoxeinvVVCQ −=CBasic LF C-Vwith gate-depletionwith gate-depletion and charge-layer thicknessVGdataCoxEffective Oxide CapacitanceEE130 Lecture 23, Slide 10Spring 2003VTAdjustment by Ion Implantation• In modern IC fabrication processes, the threshold voltages of MOS transistors are adjusted by ion implantation:– A relatively small dose NI(units: ions/cm2) of dopant atoms is implanted into the near-surface region of the semiconductor– When the MOS device is biased in depletion or inversion, the implanted dopants add to the dopant-ion charge near the oxide-semiconductor interface.oxITCqNV −=∆atomsacceptor for 0atomsdonor for 0<>IINN6EE130 Lecture 23, Slide 11Spring 2003VTAdjustment by Back Biasing• In some IC products, VTis dynamically adjusted by applying a back bias:– When a MOS capacitor is biased into inversion, a pn junction exists between the surface and the bulk.– If the inversion layer contacts a heavily doped region of the same type, it is possible to apply a bias to this pn junctionN+ poly-Sip-type Si------+ + + + + +N++ +-- -SiO2• VGbiased so surface is inverted• Inversion layer contacted by N+ region•Bias VCapplied to channelÆ Reverse bias VB-VCapplied btwn channel & bodyEE130 Lecture 23, Slide 12Spring 2003Effect of VCBon Vs, VT• Application of reverse bias -> non-equilibrium– 2 Fermi levels (one for n-region, one for p-region)• Separation = qVBCÎVsincreased by VCB• Reverse bias widens Wd, increases QdepÎQinvdecreases with increasing VCB, for a given VGBoxCBBSiABCFBTCVqNVVV)2(22++++=ψεψ7EE130 Lecture 23, Slide 13Spring 2003In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955.Invention of the Field-Effect TransistorEE130 Lecture 23, Slide 14Spring 2003Modern Field Effect Transistor (FET)• An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductor→Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrodeN-channel MOSFET:8EE130 Lecture 23, Slide 15Spring 2003Basic n-channel MOSFET structure and I-V characteristicsMOSFET I-V CharacteristicEE130 Lecture 23, Slide 16Spring 2003Two ways of representing a MOSFET:9EE130 Lecture 23, Slide 17Spring 2003Enhancement Mode vs. Depletion ModeEE130 Lecture 23, Slide 18Spring 2003N-channel vs. P-channel• For current to flow, VGS > VT• Enhancement mode: VT> 0• Depletion mode: VT< 0– Transistor is ON when VG=0VP-type SiN+ poly-Sin-type SiP+ poly-SiNMOSPMOSN+ N+ P+ P+• For current to flow, VGS < VT• Enhancement mode: VT< 0• Depletion mode: VT> 0– Transistor is ON when VG=0V10EE130 Lecture 23, Slide 19Spring 2003When Vg = Vdd, the NFET is on and the PFET is off. When Vg= 0, the PFET is on and the NFET is off.NFET PFETComplementary MOSFETs (CMOS)EE130 Lecture 23, Slide 20Spring 2003A CMOS inverter is made of a PFET pull-up device and a NFET pull-down device.C: Vin Vdd PFETNFET0V 0V S D D SVout etc.) (of interconnect, capacitanceCMOS Inverter11EE130 Lecture 23, Slide 21Spring 2003VddABABThis two-input NANDgate and many other logic gates are extensions of the basic inverter.CMOS Logic
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