1EE130 QUIZ RESULTS (UG scores only)051015202530Q1 Q2 Q3 Q4 Q5 Q6SCOREA final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans. » All of the material of the course will be covered (including HW#14) » Closed book, no calculators; 7 pages of notes allowed. Quiz 6 results:Mean = 21.69Median = 22Std. Dev. = 1.779High = 24Low = 17.5Prof. Tsu-Jae King LiuDepartment of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720May 7, 2007( More of Moore )4Issues for scaling Lgto below 20 nm:» LeakageGateSource DrainGateSource DrainGateLgThe traditional approach totransistor scaling is reachingfundamental limitshalo doping» Channel engineering» Incommensurate gains in IDsat» VTvariation» Gate oxide scaling» Shallow junctionsSiO2GateA. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002SourceDrain5Leakage must be suppressed to scale down LgLeakage occurs in region far from channel surfaceLet s get rid of it!DrainSourceGateLgThin-BodyMOSFETBuried OxideSourceDrainGateSubstrateSilicon-on-I nsulator( SOI )W afer6Leakage is suppressed by using a thin body (TSi< Lg)» Channel doping is not needed higher carrier mobility» Aggressive gate-oxide scaling is not neededDouble-gate structure is most scalable (to Lg<10nm)Ultra-Thin Body (UTB)Buried OxideSubstrateSourceDrainGateTSiLgDouble-Gate (DG)GateSourceDrainGateTSi7Lg= 12 nmTox= 2 nmUTB suppresses leakage Thick S/D => low Rseries1.E-121.E-101.E-081.E-061.E-041.E-0200.2 0.4 0.6 0.8 1Gate Voltage [V]Tsi=8nmTsi=6nmTsi=4nmSimulated Id-VgVds=1VSubthresholdswing S (units: mV/dec)M. Takamiyaet al., Proc. 1997 ISDRS, p. 215B. Yuet al. (UC Berkeley), Proc. 1997 ISDRS, p. 623Silicon SubstrateSource DrainSiO2SOIGateGate8Issues for bulk-Si MOSFET scaling obviated» Body does not need to be heavily doped» Toxdoes not need to be scaled as aggressively» Ultra-shallow S/D junction formation is not an issueBody thickness must be less than ~1/3 x Lg» Formation of uniformly thin body is primary challenge» For TSi< 4 nm, quantum confinement & interface roughness VTvariation and degraded gmK. Uchida et al., IEDM Technical Digest, pp. 47-50, 20029Planar DG-FETGateSourceDrainGateTSiFin Width = TSiLgGATESOURCEDRAIN20 nm10 nmY.-K. Choi et al. (UC Berkeley),IEDMTechnical Digest, pp. 421-424, 200115nm LgFinFET:Fin Height HFIN= W/2D. Hisamotoet al. (UC Berkeley),IEDM Technical Digest, pp. 1032-1034,1998N. Lindertet al . (UC Berkeley),IEEE Electron DeviceLetters, pp. 487-489,2001FinFETSourceDrainGateLg10gg-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-1210-1010-810-610-410-210-1210-1010-810-610-410-2N-body=2x1018cm-3P+Si0.4Ge0.6GateNMOSPMOSVd=-0.05 VVd=-1.0 VVd=0.05 VVd=1.0 V dGate Voltage, Vg [V]-1.5 -1.0 -0.5 0.0 0.5 1.0 1.501002003004005006000100200300400500600Voltage step : 0.2V|Vg-Vt|=1.2VNMOSPMOS dDrain Voltage, Vd [V]TSi= 10 nm; Tox= 2.1 nmY.-K. Choi et al. (UC Berkeley),IEDM Technical Digest, pp. 421-424, 2001Transfer CharacteristicsOutput Characteristics11ElectronMobilityHoleMobilityL. Chang et al., IEEE Trans. Electron Devices, Vol. 51, p. 1621, 2004(110)(100)(110)(110)(110)SDSD(110)PMOSSDSD(100)(100)NMOS12ggB. Yu et al. (AMD & UC Berkeley),IEDM Technical Digest, pp. 251-254, 2002220ÅSiO2 capLg=10nmBOXNiSiPoly-SiSi FinSourceDrainGate13The FinFET is attractive for high-density flash memoryFinFETSONOS Device Cross-Section30nm40nmSi3N4SiO2SiO2SiO2SiPoly-Si0FinFETSONOS Device Cross-Section30nm40nmSi3N4SiO2SiO2SiO2SiPoly-Si0P. Xuanet al.(UC Berkeley), IEDM Technical Digest, pp. 609-612, 2003Measured Retention CharacteristicsMeasured Endurance Behavior 101001k10k100k1M0.00.51.01.52.02.53.03.5Threshold voltage (V)Number of cycles (100) device (110) devicecharge-storage layerSubsequent publications:M. Spechtet al. (Infineon Technologies ), IEDM2004C. W. Oh et al. (Samsung Electronics), IEDM2004E. S. Cho et al. (Samsung Electronics), Symp. VLSI Technology200514H. Kamand T.-J. King, Proc. 2004 Silicon NanoelectronicsWorkshop, pp. 9-100400800120000.1 0.20.30.4 0.5 0.6Vds (V) Wrapped Contact, zero contact res. Wrapped Contact End ContactTop ContactVg=0.6VLg=18nm, Leff= 20nm, Wfin=10nm, Tox=5Ac=10-8 -cm2Top ContactDRAINGATESOURCEDRAINGATESOURCEEnd ContactDRAINGATESOURCEDRAINGATESOURCEWrapped ContactDRAINGATESOURCEParasitic resistance (& capacitance) will limit the performance of nanoscale CMOS Better FET designs are needed!15GS DSiclassicalmulti-gateGS DSiGhigh-gate dielectricmetallic gatestrained SiLg(nm): 50 40 30 20 10Advanced structures will enable Si FET scaling to Lg<10 nm» Minimization of parasitics will become the primary challengeforward body biasingalternativesemiconductor?larger EG, lower r16Quantum mechanical tunneling sets a fundamental scaling limit for the channel length L, to ~5 nm.SourceDrainECECIf electrons can easily tunnel through the source-to-channel potential barrier, the gate cannot shut off the transistor.J. Wang et al., IEDM Technical Digest, pp. 707-710, 2002NMOSFET Band Diagram(OFF state)( More than Moore )18innovative circuit & system designnovel semiconductor devices3-D & heterogeneous integratione.g. with micro-electro-mechanical devices (MEMS), microfluidicsAlternative approaches to » enhance performance and/or functionality» lower power consumption per functioncan help to reduce cost per functionTIME (yrs)alternativeapproachesto scaling19Texas Instruments Inc.TMTMSEM image of pixel arraySchematic of 2 pixelsMirrors are made using layers of metals (Al alloys) deposited on top of CMOS circuitryEach mirror corresponds to a single pixel, programmed by an underlying memory cell to deflect light either into a projection lens or a light absorber.20courtesy of Robert Aigner(Infineon Technologies)MEMS-enabled single-chip radioAdvantages of MEMS RF filters:small sizelow powerlow phase noisehigh QTiming reference can also be implemented on-chip with MEMSIntegration trend for mobile phonesClustersMassive ClusterGigabit Ethernetwireless sensor network21The electric field can be induced by applying a voltage across 2 electrodes sandwiching the droplethttp://www.ee.duke.edu/research/microfluidics/An electric field modifies the wetting behavior of a liquid droplet on a surface, by reducing interfacial energyIf an electric field is applied non-uniformly, then a surface-energy gradient is created, which causes the droplet to move22Multiple control
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