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Berkeley ELENG 130 - Test 4

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Test #4Name: Email: ID#UNIVERSITY OF CALIFORNIADepartment of Electrical Engineering and Computer SciencesEE130 Fall 2003Prof. SubramanianTest #41) Consider two NMOSFETs made with identical body doping, gate materials, and gate oxide thickness. MOSFET “A” has a VT of 0.5V and MOSFET “B” has a VT of 0.2V.a) Which MOSFET most likely has a shorter channel length? How do you know this?b) What phenomenon causes the difference in VT’s for the two MOSFETs?c) What is the consequence of this reduction in VT on (give reasons):i) On-current (IDsat)ii) Off-current (ID @ VGS = 0V, VDS = VDD)d) Suppose I try to reduce this VT roll-off effect. Should I increase or decrease the following parameters (give reasons)?i) toxii) rjiii) the doping right near the S/D junctionse) What is the disadvantage of reducing rj? Give your answer in terms of its impact on (give reasons)i) On-currentii) Switching speedName: Email: ID#2) Consider a MOSFET that is operating in punchthrough, as shown below.GateSDaa’a) Draw a band diagram for the MOSFET along slice a-a’. Assume the MOSFET is in flatband mode at the surface.b) We often increase the punchthrough voltage by placing a region of heavy doping (called a “halo” below the channel of the MOSFET, as shown below. HALO Why do we use a halo and not just dope the entire body more heavily. Answer the question in terms of the effect of heavy doping on:i) VTii) IONiii) MobilityName: Email: ID#3) Consider a MOSCAP with the following specifications:• The gate is a metal with a workfunction on 4.5eV• Assume silicon has an electron affinity of 4eV• The body is doped n-type such that the Fermi level is 0.2eV below the conduction band• Assume the oxide is 1.7nm thick, resulting in a Cox of 2uF/cm2.a) Draw an equilibrium band diagram for the above MOSCAP.b) What is the VFB for the above MOSCAP?c) Now, suppose we add in fixed oxide charge of 2E-7C/cm2. Redraw the equilibrium band diagramd) What is the VFB for the MOSFET


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Berkeley ELENG 130 - Test 4

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Lecture 4

Lecture 4

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MOSFETs

MOSFETs

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Exam

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PLOT.1D

PLOT.1D

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