CS 250 VLSI System Design Lecture 11 DRAM 2009 10 1 John Wawrzynek and Krste Asanovic with John Lazzaro TA Yunsup Lee www inst eecs berkeley edu cs250 CS 250 L11 DRAM UC Regents Fall 2009 UCB 1 Today s Lecture DRAM Bottom up DRAM core cells Top down SDRAM commands DRAM controller design ideas CS 250 L11 DRAM UC Regents Fall 2009 UCB 2 Dynamic Memory Cells CS 250 L11 DRAM UC Regents Fall 2009 UCB 3 Recall Capacitors in action Because the dielectric is an insulator and does not conduct I 0 After circuit settles Q C V C 1 5 Volts D cell Q Charge stored on capacitor C The capacitance of the device function of device shape and type of dielectric 1 5V After battery is removed Still Q C 1 5 Volts Capacitor remembers charge CS 250 L11 DRAM UC Regents Fall 2009 UCB 4 DRAM cell 1 transistor 1 capacitor Vdd Bit Line Word Line Word Line Vdd Capacitor Bit Line Bit Line n oxide n oxide pWord Line and Vdd run on z axis CS 250 L11 DRAM Why Vcap values start out at ground Vdd Vcap Diode leakage current UC Regents Fall 2009 UCB 5 A 4 x 4 DRAM array 16 bits CS 250 L11 DRAM UC Regents Fall 2009 UCB 6 Invented after SRAM by Robert Dennard CS 250 L11 DRAM UC Regents Fall 2009 UCB 7 www FreePatentsOnline com DRAM Circuit Challenge 1 Writing Vdd Vdd Vgs Vdd Vc Vdd Vth Bad we store less charge Why do we not get Vdd Ids W 2LD Vgs Vth 2 but turns off when Vgs Vth Vgs Vdd Vc When Vdd Vc Vth charging effectively stops CS 250 L11 DRAM UC Regents Fall 2009 UCB 8 DRAM Challenge 2 Destructive Reads Bit Line stored charge from cell initialized to a low voltage Word Line s g V 0 Vdd Vc 0 Vdd Raising the word line removes the charge from every cell it connects to Must write back after each read CS 250 L11 DRAM UC Regents Fall 2009 UCB 9 DRAM Circuit Challenge 3a Sensing Assume Ccell 1 fF Bit line may have 2000 nFet drains assume bit line C of 100 fF or 100 Ccell Ccell holds Q Ccell Vdd Vth 100 Ccell Ccell When we dump this charge onto the bit line what voltage do we see dV Ccell Vdd Vth 100 Ccell dV Vdd Vth 100 tens of millivolts In practice scale array to get a 60mV signal CS 250 L11 DRAM UC Regents Fall 2009 UCB 10 DRAM Circuit Challenge 3b Sensing How do we reliably sense a 60mV signal Compare the bit line against the voltage on a dummy bit line sense amp Bit line to sense Dummy bit line Dummy bit line Cells hold no charge CS 250 L11 DRAM UC Regents Fall 2009 UCB 11 DRAM Challenge 4 Leakage Bit Line Word Line Vdd Parasitic currents leak away charge Solution Refresh by reading cells at regular intervals tens of milliseconds n oxide pCS 250 L11 DRAM oxide n Diode leakage UC Regents Fall 2009 UCB 12 DRAM Challenge 5 Cosmic Rays Bit Line Word Line Vdd Cell capacitor holds 25 000 electrons or less Cosmic rays that constantly bombard us can release the charge Solution Store extra bits to detect and correct random bit flips ECC n oxide pCS 250 L11 DRAM oxide n Cosmic ray hit UC Regents Fall 2009 UCB 13 DRAM Challenge 6 Yield If one bit is bad do we throw chip away Extra bit lines Used for sparing CS 250 L11 DRAM Solution add extra bit lines i e 80 when you only need 64 During testing find the bad bit lines and use high current to burn away fuses put on chip to remove them UC Regents Fall 2009 UCB 14 Scaling Fundamental Cost Driver Recall The Process Scaling Recall process scaling Moore s Law Process Advances Still Scale Power 350nm 200mm 250nm 200mm CV2 Scaling Twice the circuitry in the same space architectural innovation 180nm 200mm OR 130nm 200mm The same circuitry in half the space cost reduction 90nm 300mm 65nm 300mm Dual Core Half the die size for the same capability than in the prior process 32nm 45nm 65nm 90nm 13 m 18 m 25 m 35 m 6 Due to reducing V and C length and width of Cs decrease but plate distance gets smaller Recent slope more shallow because V is being scaled less aggressively From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 2005 but the rate has slowed and collaboration is required CS 250 L11 DRAM UC Regents Fall 2009 UCB 16 15 DRAM Challenge 7 Scaling Each generation of IC technology we shrink width and length of cell As Ccell and drain capacitances scale together number of bits per bit line stays constant dV 60 mV Ccell Vdd Vth 100 Ccell Problem 1 Number of arrays per chip grows Problem 2 Vdd may need to scale down too Solution Constant Innovation of Cell Capacitors CS 250 L11 DRAM UC Regents Fall 2009 UCB 16 Poly diffusion Ccell is ancient history Bit Line Word Line Vdd Word Line Vdd Capacitor Bit Line Bit Line n oxide oxide n pWord Line and Vdd run on z axis CS 250 L11 DRAM UC Regents Fall 2009 UCB 17 Early replacement Trench capacitors CS 250 L11 DRAM UC Regents Fall 2009 UCB 18 Final generation of trench capacitors The companies that kept scaling trench capacitors are in the process of going out of business CS 250 L11 DRAM UC Regents Fall 2009 UCB 19 Modern cells stacked capacitors CS 250 L11 DRAM UC Regents Fall 2009 UCB 20 Micron 50nm 1 Gbit DDR2 die photo CS 250 L11 DRAM UC Regents Fall 2009 UCB 21 Memory Arrays Older SDRAM part 133 Mhz 128 Mb 128Mb x4 x8 x16 SDRAM SYNCHRONOUS DRAM MT48LC32M4A2 8 Meg x 4 x 4 banks MT48LC16M8A2 4 Meg x 8 x 4 banks MT48LC8M16A2 2 Meg x 16 x 4 banks For the latest data sheet please refer to the Micron Web site www micron com dramds FEATURES PC100 and PC133 compliant Fully synchronous all signals registered on positive edge of system clock CS 250 L11 DRAM Internal pipelined operation column address can be changed every clock cycle Internal banks for hiding row access precharge Programmable burst lengths 1 2 4 8 or full page Auto Precharge includes CONCURRENT AUTO PIN ASSIGNMENT Top View 54 Pin TSOP x4 x8 x16 VDD NC DQ0 DQ0 VDDQ NC NC DQ1 UC Regents Fall 2009 UCB x16 x8 x4 1 2 3 4 54 53 52 51 Vss DQ15 VssQ DQ14 DQ7 NC NC NC 22 A bank of 32 Mb 128Mb chip 4 banks 1 12 bit row address input o f 4 0 9 6 d e c o d e r CS 250 L11 DRAM 2048 columns 4096 rows 33 554 432 usable bits tester found good bits in bigger array 2048 bits delivered by sense amps Select requested bits send off the chip UC Regents Fall 2009 UCB 23 Recall DRAM Challenge 3b …