CS250 VLSI Systems Design Lecture 2 Introduction Fall 2011 Krste Asanovic John Wawrzynek with John Lazzaro and Brian Zimmer TA Lecture 02 Introduction 1 CS250 UC Berkeley Fall 11 So what has changed in 30 years Lecture 02 Introduction 1 2 CS250 UC Berkeley Fall 11 Lecture 02 Introduction 1 3 CS250 UC Berkeley Fall 11 Moore s Law Growth and Effects Lecture 02 Introduction 1 4 CS250 UC Berkeley Fall 11 Secondary driver Wafer size Processed Wafer Cost From Facing the Hot Chips Challenge Again Bill Holt Intel presented at Hot Chips 17 2005 Lecture 02 Introduction 1 Wafer size conversions offset trend of increasing wafer processing cost CS250 UC Berkeley Fall 11 5 Sourc e Intel Source 8 Processing advances 4 m Lecture 02 Introduction 1 45nm 6 CS250 UC Berkeley Fall 11 IC Technology Stuff 1 Feature size then 4 m now 032 m moving to 028 m Interconnect then 2 layers now 10 layers then aluminum now copper Transistors then planar MOSFET now same Layout and GDRs Essentially unchanged More complex Density and area fill rules Circuits then clocked static CMOS now same lots of crazy stuff in bet ween Interesting though most CMOS circuits and layouts designed in 1980 would work if fabricated on today s IC process Lecture 02 Introduction 1 7 CS250 UC Berkeley Fall 11 IC Technology Stuff 2 Transistors then near perfect switch now leaky Power consumption then dynamic switching energy now approaching 50 static leakage back to the future nMOS has similar problem New improved devices coming soon FinFETs Chip Input Output then parameter pads now often area pads Lithographic Mask Costs then few k now M full die 65 45 28nm Lecture 02 Introduction 1 8 CS250 UC Berkeley Fall 11 IC Technology Stuff 3 Device reliability then devices nearly never fail future 65nm high soft and hard error rates Process variations across die die to die Statistical variations in processing wire widths resitivity transistor dimensions strengths doping inconsistencies become apparent at smaller geometries Some circuits fast others slow Some high power some low Yield on leading edge processes dropping dramatically IBM quotes yields of 10 20 on Cell processor Lecture 02 Introduction 1 9 CS250 UC Berkeley Fall 11 Design Stuff Chip functionality then limited by area now usually limited by energy dissipation Design cost now design costs in 50M range for full die custom designs high percentage in verification Implementation Alternatives more alternatives that trade up front design costs for per unit costs FPGA compete aggressively with custom silicon then most custom designs implemented at silicon level now many more custom designs implemented with FPGAs Standard design abstraction then transistors circuits now RTL in HDLs standard cores and standard cells higher productivity somewhat less area energy efficient Lecture 02 Introduction 1 10 CS250 UC Berkeley Fall 11 Implementation Alternatives All circuits transistors layouts optimized for application Arrays of small function blocks gates FFs Standard cell automatically placed and routed Gate array Partially prefabricated wafers customized with structured ASIC metal layers or vias Prefabricated chips customized with loadable latches FPGA or fuses Instruction set interpreter customized through Microprocessor soft ware Domain Specific Special instruction set interpreters ex DSP NP GPU Processor Full custom By ASIC most people mean Standard cell based implementation What are the important metrics of comparison Lecture 02 Introduction 1 CS250 UC Berkeley Fall 11 11 The Important Distinction Instruction Binding Time When do we decide what operation needs to be performed A DeHon General Principles Earlier the decision is bound the less area delay energy required for the implementation Later the decision is bound the more flexible the device Lecture 02 Introduction 1 12 CS250 UC Berkeley Fall 11 Full Custom Circuit styles and transistors sizes are customized to optimize die size power performance High NRE non recurring engineering costs Time consuming and error prone layout Optimizing for small die can result in low per unit costs extreme low power or extreme highperformance Common for analog design Requires full set of custom masks High NRE usually restricts use to high volume applications markets or highly constrained and cost insensitive markets Lecture 02 Introduction 1 13 CS250 UC Berkeley Fall 11 Standard Cell Based around a set of pre designed and verified cells Ex NANDs NORs Flip Flops buffers Each cell comes complete with layout perhaps for different technology nodes and processes Behavioral simulation delay power models Chip layout is automatic reducing NREs usually no hand layout Requires full set of masks nothing prefabricated Non optimal use of area and power leading to higher per die costs than fullcustom Commonly used with other design implementation strategies large blocks for memory I O blocks etc Lecture 02 Introduction 1 14 CS250 UC Berkeley Fall 11 Gate Array Store prefabricated wafers of active gate layers local interconnect comprising primarily rows of transistors Customize as needed with back end metal processing contact cuts vias metal wires Could use a different factory Lecture 02 Introduction 1 15 CS250 UC Berkeley Fall 11 Gate Array Shifts large portion of design and mask NRE to vendor Shorter design and processing times reduced time to market Highly structured layout with fixed size transistors leads to large sub circuits ex Flip flops and higher per die costs Memory arrays are particularly inefficient so often prefabricated also Sea of gates structured ASIC master slice Lecture 02 Introduction 1 16 CS250 UC Berkeley Fall 11 Field Programmable Gate Arrays Two dimensional array of simple logic and interconnectionblocks Typical architecture LUTs implement any function of n inputs n 3 in this case Optional Flip flop with each LUT Fuses EPROM or Static RAM cells are used to store the configuration Here it determines function implemented by LUT selection of Flip flop and interconnection points Many FPGAs include special circuits to accelerate adder carry chain and many special cores RAMs MAC Enet PCI SERDES Lecture 02 Introduction 1 CS250 UC Berkeley Fall 11 17 Traditional FPGA versus ASIC argument circa 2000 FPGA total cost ASIC ASICs cost effective FPGAs cost effective volume ASIC High NRE costs 2M for 0 35um chip Relatively Low cost per die FPGAs Very low NRE costs Relatively low silicon efficiency high cost per part Cross over volume from cost effective FPGA design