Write and Synthesize a Two Stage Three Stage RISC V v2 Processor CS250 Laboratory 2 Version 092010a September 20 2010 Yunsup Lee For the second lab assignment you are to write an RTL model of a two stage and a three stage pipelined RISC V v2 processor using Verilog and to synthesize your RTL model After producing a working RTL model you will attempt to optimize your design to increase performance and or decrease area The deliverables for this lab are a your optimized Verilog source and all of the scripts necessary to completely synthesize your RTL implementation checked into SVN b one assembly test program and one C benchmark program to test your implementation and c written answers to the critical questions given at the end of this document The lab assignment is due at the start of class on Monday October 4 You must submit your written answers electronically by adding a directory titled writeup to your lab project directory lab2 writeup Electronic submissions must be in plain text or PDF format You are encouraged to discuss your design with others in the class but you must turn in your own work The two stage pipeline should perform instruction fetch in the first stage while the second pipeline stage should do everything else including data memory access The three stage pipeline should perform pretty similar to the two stage pipeline but the ALU operation data memory access and the branch evaluation should be done in the third stage Since the register access is done in the second stage bypass muxes are required to support back to back operations in a threestage pipeline Since RISC V does not have a branch delay slot you will need to handle branches carefully to ensure that incorrect instructions are not accidental executed If you need to refresh your memory about pipelining and the MIPS instruction set we recommend Computer Organization and Design The Hardware Software Interface Fourth Edition by Patterson and Hennessey More detailed information about the RISC V architecture can be found in the RISC V Processor Specification For more information about using Synopsys VCS for Verilog simulation consult Tutorial 4 Simulating Verilog RTL using Synopsys VCS To learn more about Synopsys Design Compiler for synthesis please refer to Tutorial 5 RTL to Gates Synthesis using Synopsys Design Compiler Detailed information about building running and writing RISC V assembly and C codes could be found in Tutorial 3 Build Run and Write RISC V Programs For this assignment you should focus on writing clean synthesizable code that follows the coding guidelines discussed in section In particular place most of your logic in leaf modules and use structural Verilog to connect the leaf modules in a hierarchy Avoid tricky hardware optimizations at this stage but make sure to separate out datapath and memory components from control circuitry The system diagram in Figure 4 can be used as an initial template for your two stage RISC V processor implementation but please treat it as a suggestion Your objective in this lab is to implement the RISC V v2 ISA not to implement the system diagram so feel free to add new control signals merge modules or make any other modifications to the system CS250 Lab Assignment 2 Version 092010a Fall 2010 2 Processor Interface riscvTestHarness testrig tohost testrig fromhost imemreq bits addr riscvProc imemreq val imemresp bits data Instruction Memory clk dmemreq rw dmemreq bits addr dmemreq bits data clk dmemreq val reset dmemresp bits data Data Memory clk Figure 1 Block diagram for RISC V v2 Processor Test Harness module riscvProc input clk reset input 7 0 testrig fromhost output 7 0 testrig tohost Testrig fromhost port Testrig tohost port must reset to zero output 31 0 imemreq bits addr output imemreq val input 31 0 imemresp bits data Inst mem port addr to fetch Inst mem port is imem request valid Inst mem port returned instruction output dmemreq bits rw output 31 0 dmemreq bits addr output 31 0 dmemreq bits data output dmemreq val input 31 0 dmemresp bits data Data Data Data Data Data mem mem mem mem mem port port port port port read or write r 0 w 1 read write address write data is dmem request valid returned read data Figure 2 Interface for RISC V v2 Processor Your processor should be in a module named riscvProc and must have the interface shown in Figure 2 We have provided you with a test harness that will drive the inputs and check the outputs of your design The test harness includes the data and instruction memories We have provided separate instruction and data memory ports to simplify the construction of the pipeline but both ports access the same memory space The memory ports can only access 32 bit words and so the lowest two bits of the addresses are ignored i e only imemreq bits addr 31 2 CS250 Lab Assignment 2 Version 092010a Fall 2010 3 and dmemreq bits addr 31 2 are significant To make an instruction memory request set imemreq bits addr to the fetch address and set imemreq val to one The data will be returned combinationally i e there are no clock edges between when a request is made and when the response returns To make a data memory request set dmemreq bits rw to zero for a load or one for a store set dmemreq bits addr to the address set dmemreq bits data to the store data if needed and finally set dmemreq val to one The data will be returned combinationally for loads while for stores the data will be written at the end of the current clock cycle Notice that the data write bus is a separate unidirectional bus from the data read bus Bidirectional tri state buses are usually avoided on chip in ASIC designs Test Harness We are providing a test harness to connect to your processor model The test harness is identical to the one described in Tutorial 4 Simulating Verilog RTL using Synopsys VCS and Tutorial 5 RTL to Gates Synthesis using Synopsys Design Compiler The test harness loads a RISC V binary into the memory The provided makefile can load both assembly tests as well as C benchmarks to run on your processor The test harness will clock the simulation until it sees a non zero value coming back on the testrig tohost register signifying that your processor has completed a test program The testrig tohost port should be set to zero on reset A very simple test program is shown in Figure 3 0x00000000 Reset vector addiw x1 x0 1 Load constant 1 into register x1 mtpcr x1 cr16 Write x1 to tohost register loop beq x0 x0 loop Loop forever Figure 3 Simple test program