Write and Synthesize a Two Stage RISC V v2 Processor CS250 Laboratory 2 Version 082511 Written by Yunsup Lee 2010 Updated by Brian Zimmer 2011 Overview For the second lab assignment you will write an RTL model of a two stage pipelined RISC V v2 a subset of the RISC V instruction set processor using Chisel and synthesize your RTL model After producing a working RTL model you will attempt to optimize your design to increase performance and or decrease area The instruction set allows for both a 32 bit or 64 bit datapath but as a 64 bit version will take more time to run through the tools we will be building a 32 bit version Deliverables This lab is due Monday September 26th at 1pm Deliverables for this lab are a your optimized and verified Chisel source and all of the scripts necessary to completely synthesize your RTL implementation checked into Git b one assembly test program and one C benchmark program to test your implementation c written answers to the questions given at the end of this document checked into git as writeup report pdf or writeup report txt You are encouraged to discuss your design with others in the class but you must turn in your own work The two stage pipeline should perform instruction fetch in the first stage while the second pipeline stage should do everything else including data memory access If you need to refresh your memory about pipelining and the MIPS instruction set we recommend Computer Organization and Design The Hardware Software Interface Fourth Edition by Patterson and Hennessey A mandatory prerequisite is to read about the RISC V architecture which can be found in the RISC V Instruction Set Manual on the website In this lab you will be implementing a subset of this instruction set but to understand what each instruction does you will need to read the relevant sections of this manual For more information about using Synopsys VCS for Verilog simulation consult Tutorial 4 Simulating Verilog RTL using Synopsys VCS To learn more about Synopsys Design Compiler for synthesis please refer to Tutorial 5 RTL to Gates Synthesis using Synopsys Design Compiler Detailed information about building running and writing RISC V assembly and C codes could be found in Tutorial 3 Build Run and Write RISC V Programs Make sure to separate out datapath and memory components from control circuitry The system diagram in Figure 3 can be used as an initial template for your two stage RISC V v2 processor CS250 Lab Assignment 2 Version 082511 Fall 2011 2 implementation but please treat it as a suggestion Your objective in this lab is to implement the RISC V v2 ISA not to implement the system diagram so feel free to add new control signals merge modules or make any other modifications to the system You will need to turn in a diagram of your datapath anyway so it is highly recommended that you draw your datapath from the beginning in a program such as Omnigraffle or Visio and keep it updated as you design This reference will be very useful to speed up debugging Processor Interface riscvTestHarness testrig tohost imem req addr testrig fromhost imem req val Cpu imem resp data Instruction Memory clk dmem req rw dmem req addr dmem req wdata clk dmem req val reset dmem resp data Data Memory clk Figure 1 Block diagram for RISC V v2 Processor Test Harness We have given you a 1 stage processor which already has a working interface to a test harness and memories The test harness will drive the inputs and check the outputs of your design for a number of tests written in assembly language These tests are targeted to verify correct functionality of every instruction The test harness includes the data and instruction memories We have provided separate instruction and data memory ports to simplify the construction of the pipeline but both ports access the same memory space The memory ports can only access 32 bit words and so the lowest two bits of the addresses are ignored i e only imemreq bits addr 31 2 and dmemreq bits addr 31 2 are significant To make an instruction memory request set imemreq bits addr to the fetch address and set imemreq val to one The data will be returned combinationally i e there are no clock edges between when a request is made and when the response returns To make a data memory request set dmemreq bits rw to zero for a load or one for a store set dmemreq bits addr to the address set dmemreq bits data to the store data if needed and finally set dmemreq val to one The data will be returned combinationally for loads while for stores the data will be written at the end of the current clock cycle Notice that the data write bus is a separate unidirectional bus from the data read bus Bidirectional tri state buses are usually avoided on chip in ASIC designs CS250 Lab Assignment 2 Version 082511 Fall 2011 3 Test Harness There are two test harnesses one for the Chisel generated emulator and another for the Chiselgenerated Verilog You should design your processor such that it passes the emulator testbench first Then when you are ready to synthesize your design you should run the Verilog testbench to ensure that there are no bugs in the Chisel verilog generator We are providing a test harness to connect to your processor model The test harness is identical to the one described in Tutorial 4 Simulating Verilog RTL using Synopsys VCS and Tutorial 5 RTL to Gates Synthesis using Synopsys Design Compiler The test harness loads a RISC V binary into the memory The provided makefile can load both assembly tests as well as C benchmarks to run on your processor The test harness will clock the simulation until it sees a non zero value coming back on the testrig tohost register signifying that your processor has completed a test program The testrig tohost port should be set to zero on reset A very simple test program is shown in Figure 2 0x00000000 Reset vector addi x1 x0 1 Load constant 1 into register x1 mtpcr x1 cr16 Write x1 to tohost register loop beq x0 x0 loop Loop forever Figure 2 Simple test program Implemented Instructions RISC V ISA is a research ISA we use in Berkeley This ISA defines 32 bit 64 bit operations including single and double precision floating point operations as well as supervisor operations Consult the RISC V Processor Specification for more details about the RISC V architecture You may also want to read Tutorial 3 Build Run and Write RISC V Programs For this lab assignment you will only be implementing the RISC V v2 subset Figure shows the 33 instructions