CS250 VLSI Systems Design Lecture 8 Introduction to Hardware Design Patterns John Wawrzynek Krste Asanovic with John Lazzaro and Brian Zimmer TA UC Berkeley Fall 2011 Lecture 8 Hardware Design Patterns CS250 UC Berkeley Fall 2011 A Difficult Design Problem A humble shift register For today s lecture we ll assume clock distribution is not an issue Lecture 8 Hardware Design Patterns 2 CS250 UC Berkeley Fall 2011 First Complication Output Stall Shift register should only move data to right if output ready to accept next item Ready What complication does this introduce Need to fan out to enable signal on each flop Lecture 8 Hardware Design Patterns 3 CS250 UC Berkeley Fall 2011 Stall Fan Out Example Ready Enable 200 bits per shift register stage 16 stages 3200 flip flops How many fanout of four gate delays to buffer up ready signal Log4 3200 5 82 6 FO4 delays This doesn t include any penalty for driving enable signal wires Lecture 8 Hardware Design Patterns 4 CS250 UC Berkeley Fall 2011 Loops Prevent Arbitrary Resizing Shift Register Module Receiving Module Ready Ready Logic We could increase size of gates in ready logic block to reduce fan out required to drive ready signal to flop enables But this increases load on flops so they have to get bigger a vicious cycle Lecture 8 Hardware Design Patterns 5 CS250 UC Berkeley Fall 2011 Second Complication Input Bubbles Sender doesn t have valid data every clock cycle so empty bubbles inserted into pipeline Valid Stage 1 Stage 2 Stage 3 Stage 4 Ready Pipeline Diagram Valid Want to squeeze bubble out of pipeline Stage 1 Valid Stage 2 Stage 3 Stage 4 Ready Lecture 8 Hardware Design Patterns Time 6 Ready CS250 UC Berkeley Fall 2011 Logic to Squeeze Bubbles Can move one stage to right if Ready asserted or if there are any bubbles in stages to right of current stage Assume same enable logic on every stage Ready Enable Valid Valid Fan in of number of valid signals grows with number of stages Fan out of each stage s valid signal grows with number of stages Longer combinational paths as number of pipeline stages grows Lecture 8 Hardware Design Patterns 7 CS250 UC Berkeley Fall 2011 A Common Design Problem Valid Stage 1 Stage 2 Stage 3 Stage 4 Ready The shift register is an abstraction of any synchronous pipelined block of logic that accepts input data and produces output data where input and output might not be ready every clock cycle How to manage growth in control logic complexity Lecture 8 Hardware Design Patterns 8 CS250 UC Berkeley Fall 2011 Solution Decouple Units with FIFOs Processing Pipeline Consumer Pipeline only cares whether space in FIFO not about whether consumer can take next value Breaks combinational path between pipeline control logic and consumer control logic For full throughput with decoupling need at least two elements in FIFO With only one element have to ping pong between pipeline enqueue and consumer dequeue Allowing both enqueue and dequeue in same cycle to single element FIFO destroys decoupling back to a synchronous connection Lecture 8 Hardware Design Patterns 9 CS250 UC Berkeley Fall 2011 Decoupled Design Discipline Many large digital designs are divided into local synchronous pipelines or units connected via decoupling FIFOs Approx 10K 100K gates per unit Decoupled units may have different clocks In which case need asynchronous FIFOs Lecture 8 Hardware Design Patterns 10 CS250 UC Berkeley Fall 2011 Hardware Design Patterns Decoupled units are an example of a design pattern Pattern Solution to a commonly recurring design problem Idea of patterns and a pattern language first proposed for building architecture Christopher Alexander Pattern language is an interlocking set of design patterns Probably better named a pattern hierarchy Alexander proposed single pattern language covering architecture from design of cities to design of roof caps Patterns popular in software engineering Gang of Four and now being used in Par Lab Our Pattern Language OPL to architect parallel software This semester continues an experiment to see if we can teach hardware design using patterns Lecture 8 Hardware Design Patterns 11 CS250 UC Berkeley Fall 2011 Digital Design Through Patterns MP3 bit string Audio Application s Berkeley Hardware Pattern Language MP3 bit string Audio Hardware RTL Lecture 8 Hardware Design Patterns 12 CS250 UC Berkeley Fall 2011 BHPL Goals BHPL captures problem solution pairs for creating hardware designs machines to execute applications BHPL Non Goals Doesn t describe applications themselves only machines that execute applications and strategies for mapping applications onto machines Lecture 8 Hardware Design Patterns 13 CS250 UC Berkeley Fall 2011 BHPL describes Machines not Applications Applications including OPL patterns Structural Patterns Pipelines Model ViewController Iteration MapReduce BHPL Machines Lecture 8 Hardware Design Patterns Computational Patterns Circuits Agent Repository Event Based Process Control Layered Systems Task Graphs N Body Methods Dense Linear Algebra Sparse Linear Algebra Unstructured Grids Graph Traversal Spectral Methods Structured Grids Dynamic Programming Graph Algorithms FSMs Graphical Models Mapping Patterns 14 CS250 UC Berkeley Fall 2011 Vocabulary for Machines Lecture 8 Hardware Design Patterns 15 CS250 UC Berkeley Fall 2011 Why a Vocabulary Need a standard graphical and textual language to describe the problems and solutions in our pattern language Really just a consistent way of drawing and talking about block diagrams Lecture 8 Hardware Design Patterns 16 CS250 UC Berkeley Fall 2011 Machine Vocabulary Machines described using a hierarchical structural decomposition Units generalized processing engines Memories Networks connect multiple entities Channels point to point connections Memories Networks Channels are specialized Units Lecture 8 Hardware Design Patterns 17 CS250 UC Berkeley Fall 2011 Unit types Memories Networks and Channels are also units just with specialized symbol to convey their main intended purpose Memories store data Networks connect multiple entities Channels are point point communication paths High level channels show primary direction of information flow Might have wires in other direction to handle flow control etc Lecture 8 Hardware Design Patterns 18 CS250 UC Berkeley Fall 2011 Hierarchy within Unit Output Port Input Port Ports shown on edge of unit Lecture 8 Hardware Design Patterns Input Output Port 19 CS250 UC Berkeley Fall 2011 Hierarchy within Memory