Simulating Verilog RTL using Synopsys VCS CS250 Tutorial 4 Version 091209a September 12 2010 Yunsup Lee In this tutorial you will gain experience using Synopsys VCS to compile cycle accurate executable simulators from Verilog RTL You will also learn how to use the Synopsys Waveform viewer to trace the various signals in your design Figure 1 illustrates the basic VCS toolflow and RISC V toolchain For more information about the RISC V toolchain consult Tutorial 3 Build Run and Write RISC V Programs VCS takes a set of Verilog files as input and produces a simulator When you execute the simulator you need some way to observe your design so that you can measure its performance and verify that it is working correctly There are two primary ways to observe your design 1 you can use display statements in your Verilog RTL to output textual trace information or 2 you can instruct the simulator to automatically write transition information about each signal in your design to a file There is standard text format for this type of signal transition trace information called the Value Change Dump format VCD Unfortunately these textual trace files can become very large very quickly so Synopsys uses a proprietary compressed binary trace format called VCD Plus VPD You can view VPD files using the Synopsys waveform viewer called Discovery Visual Environment DVE Verilog Source RTL Verilog Library RTL ASM Source Code C Source Code VCS RISC V toolchain RTL Sim RISC V Binary Execute SIM VPD Test Outputs DVE GUI Figure 1 VCS Toolflow and RISC V Assembler Toolchain CS250 Tutorial 4 Version 091209a Fall 2010 2 You will be using a simple unpipelined RISC V v1 processor as your design example for this tutorial and thus you will also learn how to build and run test codes on the processor simulator Figure 2 shows the block diagram for the example processor Figure 1 shows the RISC V toolchain which starts with an RISC V assembly file and generates a binary file suitable to run on the cycle accurate simulator This tutorial assumes you are familiar with the RISC V ISA For more information please consult the RISC V Processor Specification PC Cmp eq pc 4 rd0 rd1 Add Sign Extend 1 Control Signals rdata addr wdata Data Mem tohost en rw val Decoder Reg File op1 ir 11 0 rf wen Reg File val ir 19 15 wb sel ir 24 20 op0 pc sel Instruction Mem ir 24 20 4 branch tohost testrig tohost Figure 2 Block diagram for Unpipelined RISC V v1 Processor The following documentation is located in the course locker cs250 manuals and provides additional information about VCS DVE and Verilog vcs user guide pdf VCS User Guide vcs quick reference pdf VCS Quick Reference vcs dve user guide pdf Discovery Visual Environment User Guide vcs ucli user guide pdf Unified Command Line Interface User Guide ieee std 1364 1995 verilog pdf Language specification for the original Verilog 1995 ieee std 1364 2001 verilog pdf Language specification for Verilog 2001 ieee std 1364 2005 verilog pdf Language specification for Verilog 2005 ieee std 1364 1 2002 verilog synthesis pdf Standard for Verilog Register Transfer Level Synthesis ieee std 1800 2005 sysverilog pdf Language specification for the original SystemVerilog2005 ieee std 1800 2009 sysverilog pdf Language specification for SystemVerilog 2009 CS250 Tutorial 4 Version 091209a Fall 2010 3 Getting started You can follow along through the tutorial yourself by typing in the commands marked with a symbol at the shell prompt To cut and paste commands from this tutorial into your bash shell and make sure bash ignores the character just use an alias to undefine the character like this alias All of the CS250 tutorials should be ran on an EECS Instructional machine Please see the course website for more information on the computing resources available for CS250 students Once you have logged into an EECS Instructional you will need to setup the CS250 toolflow with the following commands source cs250 tools cs250 bashrc For this tutorial you will be using an unpipelined RISC V v1 processor as your example RTL design Create a working directory and copy files from the course locker using the following commands mkdir tut4 cd tut4 TUTROOT PWD cp R cs250 examples v riscv v1 1stage TUTROOT Before starting take a look at the subdirectories in the project directory All of your projects will have a similar structure Source RTL should be placed in the src directory and test input files should be placed in the riscv tests directory The build directory will contain all generated content including simulators synthesized gate level Verilog and final layout In this course you will always try to keep generated content separate from your source RTL This keeps your project directories well organized and helps prevent you from unintentionally modifying your source RTL There are subdirectories in the build directory for each major step in the CS250 toolflow These subdirectories will contain scripts and configuration files necessary for running the tools required for that step in the toolflow For example the build vcs sim rtl directory contains a makefile which can build Verilog simulators and run tests on these simulators For more information please consult Tutorial 2 Bits and Pieces of CS250 s toolflow You should browse the source code for the processor in src to become familiar with the design The csrc directory contains Direct C source files These C source files are used in the Verilog test harness to simulate memory parse and load ELF files Direct C is a very convenient way to glue Verilog simulation with C functions which will be used through out the course Please refer to the VCS user guide chapter 19 C Language Interface for more information on Direct C Compiling the Simulator In this section you will first see how to run VCS from the command line and then you will see how to automate the process using a makefile To build the simulator you need to run the vcs compiler with the appropriate command line arguments and a list of input Verilog files CS250 Tutorial 4 Version 091209a Fall 2010 4 cd TUTROOT build vcs sim rtl vcs full64 PP lint all noVCDE v2k timescale 1ns 10ps vc list CC I VCS HOME include define CLOCK PERIOD 1 25 define IMEM DELAY 0 4 define DMEM DELAY 0 4 src defCommon vh src riscvInst vh src riscvConst vh src riscvProcCtrl v src riscvProcDpathRegfile v src riscvProcDpath v src riscvProc v src riscvTestHarness v csrc elf cc csrc memif cc csrc main cc By default VCS generates a simulator named simv The full64 command