Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Tree and ArrayMultipliersLecture 7Required ReadingChapter 11, Tree and Array MultipliersChapter 12.5, The special case of squaringNote errata at:http://www.ece.ucsb.edu/~parhami/text_comp_arit_1ed.htm#errorsBehrooz Parhami, Computer Arithmetic: Algorithms and Hardware DesignRequired ReadingJ-P. Deschamps, G. Bioul, G. Sutter, Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems Chapter 12.1.7 FPGA Implementation of multipliers(handout distributed in class)Notationa Multiplicand ak-1ak-2 . . . a1 a0x Multiplier xk-1xk-2 . . . x1 x0p Product (a x) p2k-1p2k-2 . . . p2 p1 p0Multiplication of two 4-bit unsigned binary numbers in dot notationBasic Multiplication Equationsx = xi 2ii=0k-1p = a x p = a x = a xi 2i = = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1 i=0k-1Unsigned Multiplicationa4 a3 a2 a1 a0x4 x3 x2 x1 x0xa4x0 a3x0 a2x0 a1x0 a0x0a4x1 a3x1 a2x1 a1x1 a0x1a4x2 a3x2 a2x2 a1x2 a0x2a4x3 a3x3 a2x3 a1x3 a0x3a4x4 a3x4 a2x4 a1x4 a0x4p0p1p9p2p3p4p5p6p7p8+ax0 20ax1 21ax2 22ax3 23ax4 24Full tree multiplier - general structure7 x 7 tree multiplierA slice of a balanced-delay tree for 11 inputsTree multiplier with a more regular structureLayout of a multiplier based on 4-to-2 reduction modules2’s Complement Multiplication (1)a4 a3 a2 a1 a0x4 x3 x2 x1 x0x20232221-24-a4 a3 a2 a1 a0-x4 x3 x2 x1 x0x2023222124-a4 a3 a2 a1 a0-x4 x3 x2 x1 x0x-a4x0 a3x0 a2x0 a1x0 a0x0-a4x1 a3x1 a2x1 a1x1 a0x1-a4x2 a3x2 a2x2 a1x2 a0x2-a4x3 a3x3 a2x3 a1x3 a0x3-a0x4p0p1-p9p2p3p4p5p6p7p8+2’s Complement Multiplication (2)-a1x4-a2x4-a3x4a4x4202322212924252627282’s Complement Multiplication (3)p0p1-p9p2p3p4p5p6p7p820232221292425262728p0p1p9p2p3p4p5p6p7p820232221-292425262728- aj xi = - aj (1 - xi) = aj xi - aj = aj xi + aj - 2 ajz = 1 - z2’s Complement Multiplication (4)z = 1 - z- aj xi = - (1- aj ) xi = aj xi - xi = aj xi + xi - 2 xi- aj xi = - (1- aj xi) = aj xi - 1 = aj xi + 1 - 2-aj = - (1 - aj) = aj - 1 = aj + 1 - 2-xi = - (1 - xi) = xi - 1 = xi + 1 - 2-a4x0-a4x1-a4x2-a4x3+a4x0a4-a4a4x1a4-a4a4x2a4-a4a4x3a4-a4a4x0a4a4x2a4x1a4x3a4-1+a0x4x4-x4a1x4x4-x4a2x4x4-x4a3x4x4-x4a0x4x4a2x4a1x4a3x4x4-1-a0x4-a1x4-a2x4-a3x4a4x0a4a4x2a4x1a4x3a4-1a0x4x4a2x4a1x4a3x4x4-1292425262728a4x0a4a4x2a4x1a4x3a4-1a0x4x4a2x4a1x4a3x4x4a4x0a4a4x2a4x1a4x3a41a0x4x4a2x4a1x4a3x4x4-29-a4 a3 a2 a1 a0-x4 x3 x2 x1 x0x a4x0 a3x0 a2x0 a1x0 a0x0 a4x1 a3x1 a2x1 a1x1 a0x1 a4x2 a3x2 a2x2 a1x2 a0x2 a4x3 a3x3 a2x3 a1x3 a0x3 a0x4p0p1p9p2p3p4p5p6p7p8+Baugh-Wooley 2’s Complement Multiplier a1x4 a2x4 a3x4a4x420232221-292425262728x4a4x4a41-a4x0-a4x1-a4x2-a4x3+a4x01-1a4x11-1a4x21-1a4x31-11-1a4x0a4x1a4x2a4x3+a0x41-1a1x41-1a2x41-1a3x41-1a0x41a2x4a1x4a3x4-1-a0x4-a1x4-a2x4-a3x4a0x41a2x4a1x4a3x4-11-1a4x0a4x1a4x2a4x3292425262728a0x41a2x4a1x4a3x4-1a4x0a4x1a4x2a4x3a0x41a2x4a1x4a3x41a4x0a4x1a4x2a4x3-29-a4 a3 a2 a1 a0-x4 x3 x2 x1 x0x a4x0 a3x0 a2x0 a1x0 a0x0 a4x1 a3x1 a2x1 a1x1 a0x1 a4x2 a3x2 a2x2 a1x2 a0x2 a4x3 a3x3 a2x3 a1x3 a0x3 a0x4p0p1 p9p2p3p4p5p6p7p8+Modified Baugh-Wooley Multiplier a1x4 a2x4 a3x4a4x420232221-29242526272811Basic array multiplier5 x 5 Array MultiplierArray Multiplier - Basic CellxycincoutsFA-a4 a3 a2 a1 a0-x4 x3 x2 x1 x0x a4x0 a3x0 a2x0 a1x0 a0x0 a4x1 a3x1 a2x1 a1x1 a0x1 a4x2 a3x2 a2x2 a1x2 a0x2 a4x3 a3x3 a2x3 a1x3 a0x3 a0x4p0p1p9p2p3p4p5p6p7p8+Baugh-Wooley 2’s Complement Multiplier a1x4 a2x4 a3x4a4x420232221-292425262728x4a4x4a41Modifications in a 5 x 5 multiplierArray Multiplier – Modified Basic Cellsi-1cici+1siFAxnam5 x 5 Array Multiplier with modified cellsPipelined 5 x 5 MultiplierXilinx FPGA ImplementationEquationsZ = (2xn-1+xn-2) Y 2n-2 + … + (2xi+1+xi) Y 2i + … + +(2x3+x2) Y 22 + (2x1+x0) Y 20 (2xi+1+xi) Y = cm+1pimpi(m-1)…pi2pi1pi0 pij = xiyj xor xi+1yj-1 xor cj cj+1 = (xiyj)(xi+1yj-1) + (xiyj)cj + (xi+1yj-1)cjModified Basic CellXilinx FPGA Implementationcj+1cipijFAyjxixi+1yj-1LUT0 1xiyicj+1cjpijxi+1yi-1Modified Basic CellXilinx FPGA ImplementationLUT: xiyj xor xi+1yj-1 pij = xiyj xor xi+1yj-1 xor cjcj+1 = (xiyj)(xi+1yj-1) + (xiyj)cj + (xi+1yj-1)cjXilinx FPGAMultiplierOptimizations for Squaring (1)Optimizations for Squaring (2)xi xjxj xixi xjxi xjxixi xjxi xjxi xj + xi xj = 2 xi xjxi xj + xi = 2 xi xj - xi xj + xi = = 2 xi xj + xi (1-xj) = = 2 xi xj + xi xjxi xi = xiSquaring Using Look-Up Tablesfor relatively small values kinput=aoutput=a201232k-10149(2k-1)24 16ii2. . .. . .2k words 2k-bit eachMultiplication Using Squaringa x = (a+x)2 -
View Full Document
Unlocking...