Project Specifications: A. Names of all team members Swapna Dondapati, Sudha Kode B. Title of the project Single Precision Floating Point Addition according to ANSI/IEEE 754 standard. C. Introduction Developed to address the problem of trade off between accuracy and dynamic range in fixed point notation Floating Point arithmetic has become ubiquitous today and many scientific applications rely on this. So in spite of its complexity when implemented on FPGA’s many applications use it as they • Provide Dynamic range of representation from the very small to the very large numbers. • Provide High-levels of accuracy during the calculations. • Speed up of calculations by performing millions of calculations per second. D. Implemented arithmetic unit • Function: Floating point addition. • Types and sizes of all operands: numbers of length 32 bits. E. Real-life application of a given arithmetic unit Image and digital signal processing applications typically require high calculations throughput. The arithmetic operators such as floating point addition/subtraction were implemented for real time signal processing on the Splash-2, which includes a 2-D fast Fourier transform (FFT) and a systolic array implementation of a FIR filter. Such signal processing techniques necessitate a large dynamic range of numbers. The use of floating point helps to alleviate the under flow and overflow problems often seen in fixed point formats. In order to implement an FFT on Splash-2, Floating point arithmetic adder/subtract or and multiplier units were selected to satisfy the numerical dynamics of this application. Until recently, any meaningful floating-point arithmetic has been virtually impossible to implement on FPGA’s based systems due to the limited density, routing resources and speed of older FPGA’s. In addition mapping difficulties occurred due to the inherentcomplexity of floating point arithmetic. With the introduction of high level languages such as VHDL, rapid prototyping of floating point formats has become possible making such complex structures more feasible to implement. F. Optimization criteria • maximum throughput G.Interface Overflow(fovf) X Underflow(fundf) Zero(fzero) Y clk Z(result) Input: X,Y std_logic_vector (31 down to 0). Clock:std_logic. Output: fovf, fundf, fzero std_logic. Z std_logic-vector (31 down to 0). H. Software implementation used to generate test vectors. C programming Language.I. Test plan • number and types of test vectors About 10 to 12 floating point inputs for showing different conditions of outputs for example overflow underflow, zero conditions. • Test for Critical path: the test vector, which triggers the critical path. J. Language, Platform, and Tools • hardware description language: VHDL • platform: Xilinx FPGAs • HW tools: Aldec Active-HDL + Synplicity Synplify Pro + Xilinx ISE • SW tools: K. List of references describing Behrooz Perhami, Computer Arithmetic, Algorithms and Hardware Designs. Isreal Koren, Computer Arithmetic Algorithms. Implementation of IEEE single precision floating point addition and multiplication on FPGAs Louca, L.; Cook, T.A.; Johnson, W.H.; FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on , 17-19 April 1996 Page(s): 107 -116 An Analysis of Floating Point addition D.W.Sweeney IBM systems Journal, Vol 1 .No 1,1965. An FPGA Implementation Of the Floating Point addition Chokri Souani, Mohamed Abid & Rached Tourki 1998 Proceedings. IEEE Symposium Page(s): 1644 –1648. Quantitative analysis of floating point arithmetic on FPGA based custom computing machines. Nabeel Shirazi, Peter M. Athanas, and A. Lynn Abbott IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95) April 19 - 21, 1995 Napa Valley, California . Implementation of a 2-D Fast Fourier Transform on a FPGA-Based Custom Computing Machine Nabeel Shirazi, Peter M. Athanas, and A. Lynn Abbott Virginia Polytechnic Institute and State University Bradley Department of Electrical Engineering Blacksburg, Virginia
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