ECE 645 Midterm Exam 2 (15 points) Version II For students taking the exam on Sunday and Monday, May 2 and 3. Due date for an electronic or fax submission of the solutions: Monday, May 3, 11:59 PM E-mail: [email protected] Fax number: (703) 993-1601 Due date for the submission of solutions on a CD or on paper Tuesday, May 4, 8:00 AM S&T II, room 223 (please slide your solutions under the door, or leave them in the ECE Office) Instructions: Please solve the problem from Option I for Designers OR Option II for Analysts. Please submit your solution for ONE option ONLY.Option I for Designers (15 points) Develop and debug a synthesizable Register Transfer Level (RTL) VHDL (or Verilog) code for the unsigned nonrestoring array divider built of controlled add/subtract cells (shown in Parhami, Fig. 15.8 for the case of k=3). The divider should support a 2k-bit fractional dividend and a k-bit fractional divider. Your circuit should check for an overflow condition, and have an overflow output. Perform the following tasks: 1. Check the functionality of your circuit for k=4 and k=12 using at least three different test vectors in each case. 2. Set the target FPGA device to Spartan 2, XC2S100-5TQ144C. Synthesize your codes for k=4 and k=12 using Synplify Pro, and implement them using Xilinx ISE. Perform the timing simulation of your circuit using the same test vectors you used for the functional simulation. Check thoroughly all implementation reports. 3. For both versions of your circuit (with k=4 and k=12), determine their minimum latency and the number of CLB slices required for their implementation. Deliverables: 1. source codes of the o main circuit o test circuit (if any) o testbench 2. waveforms demonstrating the correct timing simulation of your circuits at their maximum clock frequency for three different test vectors 3. short report containing at least the description of the o circuit interface o test vectors o minimum number of CLB slices o minimum latency. Option II for Analysts (15 points) Parhami, Problem 18.5 b and c, and Problem 18.6 a and b, Leading zeros/ones
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