Introduction:Implemented Arithmetic Units:Real-life application of a given arithmetic unit:Optimization criteria:Interface:ECE 645 32 Bit Squarer and Variable Rotator for Implementation of RC6 Block Cipher Milind M. Parelkar Nandakishore SastryIntroduction: One of the arithmetic operations in the RC6 Block Cipher involves computation of the function t = B (2B+1) <<< log2 w, where B is a 32-bit block of plaintext and w is the word size (32 bits) [1]. This function can be implemented as t = (2B2+B) <<< 5. The function (2B2+B) is computed modulo 232 and the result is rotated left by 5 bit positions. This operation will be performed using a squarer (mod 232), the output of which will be rotated left by 5 bits. A similar operation is performed on another 32-bit block of plaintext, D to obtain u = (2D2+D) <<< 5. The operation A = ((A ⊕ t) <<< u) + S [2i] is performed on A, where A is a 32-bit block of plaintext and S[2i] is a w-bit round key. The above operation involves computing (A xor t) and rotating it left by log2 w least significant bits of u, i.e. by 5 least significant bits of u. This will be computed using a variable rotator. Similarly, another operation C = ((C ⊕ u) <<< t) + S [2i+1] is performed on another 32-bit block of plaintext C. The goal of the project is to implement these functions using a minimum area squarer and a variable rotator. Implemented Arithmetic Units: A. Arithmetic Unit to compute ((2B2+B) mod 232 )<<<5 which includes • A minimum area 32 bit squarer to compute B2. The squarer computes the result in a single clock cycle. None of the implemented units will be pipelined. • A minimum area 32 bit adder to compute (2B2)mod 232+B B. A minimum area Variable rotator to perform the rotate left operation by a variable number of bit positions (0 to 31) The block diagrams for these arithmetic units are shown below Fig 1: 32-bit Squarer (mod 232) and 32-bit adder. Fig 2: Variable rotatorReal-life application of a given arithmetic unit: These arithmetic units are used in the computation of arithmetic operations involved in the RC6 encryption algorithm. Optimization criteria: The computation of the function t = B (2B+1) <<< log2 w involves a multiplication operation. Instead of implementing this function using a multiplier, the function will be implemented using a squarer [4]. The optimization criteria will be to achieve a non-pipelined minimum area squarer which computes the result in a single clock cycle and variable rotator. This will ultimately contribute to the minimum area implementation of RC6 encryption algorithm. Interface: 1. 32-bit Squarer and associated arithmetic logic to implement the function t = (2B2+B) <<< 5. – (Component 1) 2. Variable rotator – (Component 2) X is the number which is to be rotated by Y. ENTITY PORTS MODE WIDTH B IN 32 Component 1 t OUT 32 X IN 32 Y IN 5 Component 2 Z OUT 32Software implementation used to generate test vectors: Own implementation in C/C++ will be used to generate test vectors for verification of the implemented arithmetic units. Test Plan: 32 bit test vectors will be stored in a multi-dimensional array in the testbench. Test vectors will include those which trigger the critical path in the circuit. Also, some random test vectors will be used to verify the correct operation of the circuit. Sample test vectors for the unit implementing the function t = (2B2+B) <<< 5 are given below B: 0xFFFFFFFF t: 0x00000020 B: 0xFF123123 t: 0xF8E0D6AA B: 0xFFFF0000 t: 0xFFE0001F B: 0x99000099 t: 0xA016EF6B B: 0x897ABCDE t: 0xEB0BBCDB B: 0x00000001 t: 0x00000060 B: 0x10000000 t: 0x00000002 B: 0x00000020 t: 0x00010400 B: 0x80000001 t: 0x00000070 B: 0xBCD2341C t: 0xBD1F4781 Sample test vectors for the variable rotator are given below X: 0x0000FFFF Y: 0x1F Z: 0x80007FFF X: 0x0000FFFF Y: 0x1E Z: 0xC0003FFF X: 0x0000FFFF Y: 0x1C Z: 0XF0000FFF X: 0x0000FFFF Y: 0x1F Z: 0x80007FFF X: 0x0000FFFF Y: 0x01 Z: 0x0001FFFE X: 0xFFFFFFFF Y: 0x1F Z: 0xFFFFFFFF X: 0x00010000 Y: 0x00 Z: 0x00010000 X: 0x0000FFFF Y: 0x1F Z: 0x80007FFF X: 0x11111111 Y: 0x1B Z: 0x88888888 X: 0x99999999 Y: 0x18 Z: 0x99999999Language, Platform and Tools • Language: VHDL • Platform: Xilinx FPGAs. • Hardware Tools: o Simulator: Aldec Active HDL v.6.2 o Synthesis Tool: Synplify Pro v.7.3.4/Xilinx XST o Implementation Tool: Xilinx ISE 6.x • Software Tool: Visual Studio 6.0 List of References: 1. Ronald L. Rivest, M.J.B Robshaw, R. Sidney, Y. L. Yin, The RC6 Block Cipher v1.1, August 20, 1998 2. B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs, 1999 3. P. Chodowiec, Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware, Master's Thesis, March 2002. Available at http://ece.gmu.edu/crypto/publications.htm 4. A.J. Elbirt, W Yip, B Chetwynd, C Paar, An FPGA Implementation and Performance Evaluationof the AES Block Cipher Candidate Algorithm
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