ECE 645 Project 2 Specifications Area Optimized Square Root and Divider Unit for Multimedia Processing Applications Shilpa Reddy & Utkarsh SrivastavaIntroduction: Digital systems for square root computation and division are still a challenge for IC designers. Various techniques have been proposed for increasing division/square root performance, including staging of simple low-radix stages, overlapping sections of one stage with another stage and prescaling the input operands. All of these methods introduce area-performance tradeoffs. Here, we consider Newton-Raphson’s Method with 32-bit input, which calculates the square root and quotient directly. We can achieve low latency with a relatively small amount of hardware, as the number of iterations for square root computation is minimal. Implemented arithmetic Unit: Function: Following the Newton-Raphson method, the square root of a number is computed through the iterative formula, x (k+1) = 0.5 [x(k) + (a/x(k))] In general, C = Sqrt (A) & C = A/B Types & Sizes of Operands: Input: Dividend: 32 bits Divisor: 16 bits Output: Quotient: 16 bits Square root: 16 bits Control Signals: Clock Reset Real-Life Applications: Division and square root are important operations in many high performance graphics and multimedia processing. Multimedia processing is becoming increasingly important with a wide variety of applications ranging from multimedia cell phones to high-definition interactive television. Media processing involves the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2-D/3-D graphics, animation, and full-motion video. All these applications require fast processing of arithmetic operations with area optimization, which can be achieved by multitasking operations using a single unit. Optimization Criteria: Implementation of an iterative algorithm to compute square-root/division would result in small area, which is apt for high performance multimedia processing applications. So goal is to achieve low area with multiple tasks.Interface: Control Signals: Reset: in STD_LOGIC; Square_Root/Division: in STD_LOGIC; Start_Calculation: in STD_LOGIC; End_Calculation: out STD_LOGIC; Data Signals: A: in STD_LOGIC_VECTOR (31 downto 0); Divisor: in STD_LOGIC_VECTOR (16 downto 0); Square_Root / Quotient: out STD_LOGIC_VECTOR (16 downto 0); ClockA / Dividend [31:0] Square-root / Divider Unit Reset Square_Root / Division Square_Root (A) / Quotient [16:0] Start_Calculation Divisor [16:0] End_CalculationSoftware Implementation Used to generate test vectors: The test vectors will be generated from standard square-root/division operation of C, C++ or Java Programming language. Test Plan Test vectors will be read from an input file, which will stimulate circuit inputs. It will include those, which trigger the critical path in the circuit, & some random test vectors will be used to verify the correct operation of the circuit. Language, Platform and Tools: • Hardware Description Language: VHDL • Platform: Xilinx FPGAs • HW tools: Aldec Active-HDL + Synplicity Synplify Pro + Xilinx ISE + Synopsys • SW tools: Java or C, C++. List of References: • “Square Root on Chip”, Borisav Jovanović, Milunka Damnjanović and Vančo Litovski • “Low Power Division and Square Root”, Univeristy of California, by Alberto Nannarelli, 1999 • “Computer Arithmetic: Algorithms and Hardware Designs”, Parhami, Behrooz, New York 2000 • “A Survey of Media Processing Approaches”, A. Dasu and S. Panchanathan, Fellow, IEEE August
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