ECE 645 Project Specifications DraftArea Efficient Hardware Implementation of IDEA (International Data Encryption Algorithm) ECE 645 Project Specifications Draft Sukhonthip Rueangvivatanakij Deepashree R IyerIntroduction IDEA (International Data Encryption Algorithm) is a block cipher that belongs to a class of cryptosystems called secret-key cryptosystems, which is characterized by the symmetry of encryption and decryption processes. It encrypts 64-bit plaintext to 64-bit ciphertext blocks, using a 128-bit input key K. It consists of 8 computationally identical rounds followed by an output transformation (see Figure 7.11 in [2]). Round r uses six 16-bit subkeys Kri, 1≤ i ≤ 6, to transform a 64-bit input X into an output of four 16-bit blocks, which are input to the next round. The round 8 output enters the output transformation, employing four additional subkeys Ki9, 1≤ i ≤ 4 to produce the final ciphertext Y= (Y1, Y2, Y3, Y4) .All subkeys are derived from K. The designs philosophy behind IDEA is to mix operations from different algebraic groups including XOR, addition modulo 216, and multiplication modulo 216+1.All these operations operate on 16-bit sub-blocks. Thus, it’s efficient even on 16-bit processors. Each round consists of 4 addition modulo 216 blocks, 4 multiplication modulo 216+1 blocks and 6 XOR blocks. Implementation of Arithmetic Unit • Addition modulo 216 of 16-bit integers X and K Represented as (X + K) mod 216 • Multiplication modulo 216+1 of 16-bit integers X and K Represented as (X * K) mod 216+1 • Multiplicative Inverse of 16-bit integer K (using Extended Euclidean Algorithm) Represented as K-1, where (K-1* K) mod 216+1 = 1 Type of the operands Input Message size: 64-bit Std_logic_vector Key size: 128-bit Std_logic_vector Output Ciphertext: 64-bit Std_logic_vector Control Unit: A control unit would be designed to produce the following signals - 1-bit Start/End signal - 4-bit Std_Logic_Vector representing the Round Number - 1-bit Encryption /Decryption Signal Real-life application of a given arithmetic unit • Real life applications like Pretty Good Privacy (PGP) and Secure Socket Layer (SSL) use block ciphers like IDEA to encrypt the messages. • Primitive algebraic groups like 216+1 modulo multiplication and 216 modulo addition are the basic building blocks of cryptographic algorithm such as IDEA. Optimization Criteria In most of the published research papers about IDEA implementation emphasis was on achieving maximum throughput. While focusing the attention on the speed, the area consumption by the designincreased due to feature like pre-computation of the keys and parallel processing. But there are applications were the resource such as area is limited and at the same time requiring optimum throughput. Hence, in this project we focus on the “Area Efficient hardware implementation of IDEA” and at the same time trying to keep the speed to at least 100Mb/sec. Interface For each Addition modulo 216 and Multiplication modulo 216+1 blocks Input Ports • 16-bit Round Key, Std_logic_vector • 16-bit Input, Std_logic_vector Output Port • 16-bit Output, Std_logic_vector For the Multiplicative Inverse block Input Ports • 16-bit Round Key (used for encryption), Std_logic_vector Output Port • 16-bit Round Key (used for decryption), Std_logic_vector Software Implementation used to generate test vectors We are planning to use public domain software implementation of IDEA to check and compare the ciphertext produced by the hardware implementation. Tentative Test Plan First we generate the cipher text using the software implementation. Test bench of the hardware implementation would be designed in such a way that it compares the cipher texts produced by the software and hardware implementation, if they don’t match, the test bench would generate the error message and the location of the error. If time permits, we would design the test bench to check the intermediate results of each arithmetic unit. Language, Platform and Tools Design Entry method: VHDL Target Implementation: Xilinx, Spartan3 CAD tools used: Active HDL 6.1, Synplify Pro 7.2, Xilinx ISE 6 Software Tools: Microsoft Visual C++ References [1] http://www.pasta.cs.uit.no/thesis/html/ronnya/node16.html. [2] Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, Handbook of Applied Cryptography, CRC Press, Inc., Boca Raton, 1996[3] William Stallings, Cryptography and Network Security: Principles and Practice, 2nd ed., Prentice Hall, Upper Saddle River, 1999. [4] Bruce Schneier, Applied Cryptography : Protocols, algorithms and source code in C, 2nd ed., John Wiley & Sons, Inc. [5] Yi-Jung Chen, The Research and Design of a High Performance IDEA Chip, Master Thesis report, National Chi Nan University, June 2002 [6] Irwin Yoon, Implementation of IDEA (International Data Encryption Algorithm) in C++, http://islab.oregonstate.edu/koc/ece575/03Project/Yoon/ [7] Johannes Wolkerstorfer, Dual-Field Arithmetic Unit for GF(p) and GF(2m), Institute for Applied Information Processing and Communications, Graz University of Technology, Inffeldgasse 16a, 8010 Graz, Austria. [8] O.Y.H.Cheung, K.H.Tsoi, P.H.W.Leong and M.P.Leong, Tradeoffs in parallel and serial implementations of the International Data Encryption Algorithm IDEA, CHES 2001, LNCS 2162, pp. 333-347. [9] Reto Zimmermann, Efficient VLSI implementation of Modulo (2n±1) addition and multiplication. [10] R.Zimmermann, A.Curiger, H.Bonnenberg, H.Kaeslin, N.Felber, and W.Fichtner, A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm, IEEE Journal of Solid-States circuits, Vol.29, No.3, March 1994. [11] R.Zimmermann, A.Curiger, H.Bonnenberg, H.Kaeslin, N.Felber, and W.Fichtner, VINCI: VLSI implementation of the new secret- key block cipher IDEA, IEEE custom integrated circuits conference,