Professor: Kris GajTeam MembersTable of ContentsIBM PowerPC 440Software implementation in Perl will be used initially to inGeorge Mason University ECE 645 Project 2 Specification Multiplier-Accumulator (MAC) Professor: Kris Gaj Team Members Jamie Bernard George Michael April 17th 2004Table of Contents 1. Introduction / Abstract 2. Implemented Arithmetic Unit 3. Real Life Application 4. Optimization Criteria 5. Interface 6. Test Plan 7. Tools 8. References 21. Introduction / Abstract The motivation for choosing this project topic is that Digital Signal Processing (DSP) has become intertwined in our daily lives, whether it is through receiving a phone call on a cell phone, watching a DVD, or accessing the internet via a cable modem. These DSP applications require immediate results from mathematically intensive algorithms. Even IBM’s PowerPC 440 series have added instruction sets to the architecture to support DSP functions for increased processing speed. Being able to multiply and accumulate (MAC) is a fundamental operation performed by general purpose DSPs and microprocessors. Designing a MAC in hardware allows for the construction of many DSP functions such as FIR low-pass filter. By investigating techniques that reduce latency and area, more sophisticated DSP functions can be achieved as well as obtaining crucial real estate on a microprocessor. 2. Implemented Arithmetic Unit -Function: 64 bit signed multiplier-accumulator (MAC) which will accumulate 256 partial products -Types and sizes of all operands: A=> 64 bit signed std_logic_vector input B=> 64 bit signed std_logic_vector input C=> 136 bit signed std_logic_vector output Carry Out=> 1 bit std_logic -Control Signals: Clock Reset Start Finish 3C = ∑ Αι ∗ ΒιA B 64 64 Multiplier 3. Real Life Applications IBM PowerPC 440 136ACC REG+136136C Digital Filters Fir Filters IIR Filters Radar Audio Signal Processing Cable Modem The MAC unit developed for this project will be very similar to the one used on the Motorola DSP560xx processors or could replace the software version with FPGA hardware for the Philips XA microcontroller. These ASICs use MAC units for DSP algorithms including creating digital low pass FIR filters. 44. Optimization Criteria The design will center on the following criteria: -Minimum Area -Minimum Latency Since these optimization criteria are negatively correlated, the goal of this project will be to limit the area to a LUT count of 60-70% of the total LUTs on a given FPGA. Once this goal is obtained, the MAC design will be optimized for minimum latency. 5. Interface 136 Bits64 Bits 64 Bits MAC Top LevelA A CB Carry OutStart Clk Reset Finish 56. Test Plan Software implementation in Perl will be used initially to insure general functionality of the MAC. Then known test vectors which exercise the critical path will be generated using the Perl MAC algorithm. Pattern coverage will be increased using a random pattern generator inside of the testbench. This will insure that the output of the MAC entity has greatest total pattern coverage as well as correct operation. The function of the testbench will be to calculate the correct output of the MAC independently and compare that result to the actual output obtained from the MAC via the Perl script and random pattern generator. Discrepancies between the results will be identified in the simulation interface. 7. Tools -VHDL will be used as the hardware description language. -Platform: Xilinx FPGA’s -Hardware Tools: Simulation: ModelSim 5.8 Synthesis: Synplify Pro Implementation: Xilinx ISE -Software Tools: Perl 8. References [1] I. Koren, “Computer Arithmetic Algorithms,” 2nd edition, A K Peters Ltd., Massachusetts 2000. [2]B. Parhami, “Computer Arithmetic: Algorithms and Hardware Designs,” Oxford University Press, New York 2000. [3] Lecture Notes from Dr. Gaj for ECE645-GMU – Spring 2004. [4] Xilinx website; http://www.xilinx.com/ [5] Booth, A Signed Binary Multiplication Algorithm, Qt. J. Mech. Appl. Math., vol. 4, pp. 236-240, 1951. 6[6] Berkeley Design Technology Inc., “Choosing a DSP Processor” 1996-2000. [7] Philips Semiconductors, “Digital Filtering using XA” Mar 1996.
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