VLSI Design Automation of a Montgomery Multiplier using Astro by SynopsysOverviewRSA Public-Key CryptosystemMontgomery MultiplicationVery Large Scale Integration (VLSI)Application Specific Integrated Circuits (ASIC)Astro – Place and Route ToolAstro TutorialAstro TutorialMontgomery Multiplier Circuit SynthesisMontgomery Multiplier Circuit Synthesis – Library and Cell CreationMontgomery Multiplier Circuit Synthesis – Library and Cell CreationMontgomery Multiplier Circuit Synthesis – Optimizations and PlacementMultiplier Cell after PlacementMontgomery Multiplier Circuit Synthesis – RoutingMultiplier Cell after RoutingAdditional Astro ToolsMultiplier Clock TreeMultiplier Voltage Drop MapMontgomery Multiplier Circuit Synthesis – Timing ReportsMontgomery Multiplier Timing ResultsMontgomery Multiplier Timing ResultsConclusionsQuestions ?VLSI Design Automation of a VLSI Design Automation of a Montgomery Multiplier using Montgomery Multiplier using Astro by Astro by SynopsysSynopsysSteven Hubbard Steven HubbardOverviewOverviewMontgomery Multiplier for RSA EncryptionMontgomery Multiplier for RSA EncryptionPhysical Design Physical Design ––ASIC and ASIC and SoCsSoCsASIC AdvantagesASIC AdvantagesAstro Place and Route by Astro Place and Route by SynopsysSynopsysMontgomery Multiplier Circuit SynthesisMontgomery Multiplier Circuit SynthesisResultsResultsRSA PublicRSA Public--Key CryptosystemKey CryptosystemDeveloped by Developed by RivestRivest, , ShamirShamir, and , and AdlemanAdlemanin 1978in 1978Private Key contains two large prime Private Key contains two large prime numbers, numbers, ppand and qq, as well as a secret , as well as a secret exponent exponent ddPublic Key consists of n = Public Key consists of n = pp* * qq, with , with exponent exponent eeRequires Modular ExponentiationRequires Modular ExponentiationDecryption involves larger exponentiationDecryption involves larger exponentiationMontgomery MultiplicationMontgomery MultiplicationEfficient technique for computing modular Efficient technique for computing modular exponentiations exponentiations Does not require division in taking Does not require division in taking modulusmodulusReplaces with bit shifting, which is fast and Replaces with bit shifting, which is fast and easy in hardwareeasy in hardwareSimple conversion to Montgomery Domain Simple conversion to Montgomery Domain done before and after Multiplicationdone before and after MultiplicationVery Large Scale Integration (VLSI)Very Large Scale Integration (VLSI)Computer Aided Design of Complex Computer Aided Design of Complex CircuitsCircuitsTools for VLSI Produced by Tools for VLSI Produced by SynopsysSynopsysUsed for Application Specific Integrated Used for Application Specific Integrated Circuits (ASIC) and Systems On Chips Circuits (ASIC) and Systems On Chips ((SoCsSoCs))Application Specific Integrated Application Specific Integrated Circuits (ASIC)Circuits (ASIC)AdvantagesAdvantagesSpeedSpeedAreaAreaPower ConsumptionPower ConsumptionDisadvantagesDisadvantagesManufacturing Time (FPGA time about half)Manufacturing Time (FPGA time about half)CostCostAstro Astro ––Place and Route ToolPlace and Route ToolCreates Physical Design LayoutCreates Physical Design LayoutUses 3 Primary InputsUses 3 Primary InputsGate Level Gate Level NetlistNetlistfrom from VerilogVerilogStandard Cell Library of Target TechnologyStandard Cell Library of Target TechnologyAlso contains timing information for the cellsAlso contains timing information for the cellsDesign Constraints (SDC File)Design Constraints (SDC File)Clock SpeedsClock SpeedsInput / Output DelaysInput / Output DelaysAstro TutorialAstro TutorialProvided by Provided by SynopsysSynopsysPrimary Resource for ProjectPrimary Resource for ProjectTutorial Version: 3.6Tutorial Version: 3.6Designed for Astro Version: 2003.09Designed for Astro Version: 2003.09--SP1SP1Astro Version in Lab: 2004.06Astro Version in Lab: 2004.06--SP1SP1Used same steps for Montgomery Used same steps for Montgomery Multiplier Circuit SynthesisMultiplier Circuit SynthesisAstro TutorialAstro TutorialConsists of 12 section which step through Consists of 12 section which step through placeplace--andand--route and other tools.route and other tools.Not all sections used, not needed for Not all sections used, not needed for circuit.circuit.Will be a primary resource for ECE 681 Will be a primary resource for ECE 681 ––VLSI Design Automation class.VLSI Design Automation class.Montgomery Multiplier Circuit Montgomery Multiplier Circuit SynthesisSynthesisVHDL CodeVHDL CodeProvided by Hoang LeProvided by Hoang LeMontgomery Multiplier Used in Elliptic Curve Montgomery Multiplier Used in Elliptic Curve Method CircuitMethod CircuitUse Design Analyzer in on Unix Server to Use Design Analyzer in on Unix Server to convert to convert to VerilogVerilogand create SDC Timing and create SDC Timing FileFileMontgomery Multiplier Circuit Synthesis Montgomery Multiplier Circuit Synthesis ––Library and Cell CreationLibrary and Cell CreationFirst steps in AstroFirst steps in AstroCreate LibraryCreate LibraryExpand Expand NetlistNetlistfrom from VerilogVerilogCodeCodeLink Technology files and Reference Link Technology files and Reference LibraryLibraryTechnology File Technology File --designs.tlu.18.tf designs.tlu.18.tf Reference Library Reference Library --tcbn90gtcbn90g90 nm circuit90 nm circuitLoad Timing Constraints from SDC FileLoad Timing Constraints from SDC FileMontgomery Multiplier Circuit Synthesis Montgomery Multiplier Circuit Synthesis ––Library and Cell CreationLibrary and Cell CreationCreate CellCreate CellPower / Ground RingPower / Ground RingP/G StrapP/G StrapStandard CellsStandard CellsMontgomery Multiplier Circuit Synthesis Montgomery Multiplier Circuit Synthesis ––Optimizations and PlacementOptimizations and PlacementPre and Post Placement OptimizationPre and Post Placement OptimizationFrequent Optimizations run throughout Frequent Optimizations run throughout process to lower delay and verify designprocess to lower delay and verify designPlace BlocksPlace BlocksArrange Standard CellsArrange Standard CellsCreate Clock Tree SynthesisCreate Clock Tree SynthesisDrive all clocked components without Drive all clocked components without connecting them to a single port.connecting them to a single