ECE 645 Project 2 Specification: A. Name: Steven Hubbard B. Title: 64-Bit Signed Multiplier-Accumulator (MAC) C. Introduction: This project is to explore different ways of implementing a 64-bit signed multiplier-accumulator (MAC) for different uses in digital filters or DSP’s. Digital signal processors are used in most multi-media electronics including communications, audio, video, navigation, and control. Therefore, as one of the base elements in digital signal processing, the multiplier accumulator can be developed in different ways according to the specifications of a given application. D. Implemented arithmetic unit: The MAC will multiply and add a sequence of numbers according to the following equation: where N is the length of the sequence. Then the MAC will accumulate N partial products, up to 256, and permit parallel read out of the sum. The structure of the circuit is shown below, with additional registers included before and after the multiplier for better pipelining.E. Real-life application of a MAC: The primary purpose of MAC’s is for increasing performance in digital signal processing. DSP uses include various audio, wireless, and networking applications and are an increasingly large section of the semiconductor market. Because of the diverse ways MAC’s are used the requirements of cost, area, power consumption, throughput, and latency are different depending on the specific application of the DSP. For this application I will be developing for graphics image processing of a single picture, such as for a high definition digital camera. F. Optimization Criteria: For this project I will first try to decrease latency with a secondary goal of area because the pictures will not be repeating quickly, but the speed at which they are processed is very important. I will not be concerned with cost or power consumptions, but I will be adding a few registers for pipelining, to help increase throughput, although it is not my primary goal. G. Interface: A : in signal 64 bit B : in signal 64 bit CLK : in signal 1 bit START : in signal 1bit STOP : in signal 1 bit DONE : out signal 1 bit Q : out signal 384 bit H. Software implementation used to generate test vectors: Will try and find a suitable public domain implementation but will probably have to modify to some degree. I. Test Plan: The test benches will need to test the circuit to find the critical paths of the circuit that will most affect latency. Therefore there will be a few tests for simple functionality, a test for each critical path, and then a final test of all “1”s to see if it is the worst case scenario. J. Language, Platform, Tool: The code will be written in VHDL. The code will be written with Aldec Active-HDL and simulated with ModelSim. Because of the size of the design it will be implemented on the Vertex II FPGA. Then it will also be tested on the ASIC TSMC to compare the two platforms. K. References: Behrooz Parhami: Computer Arithmetic Algorithms and Hardware Designs; Oxford University Press, 2000 http://teal.gmu.edu/courses/ECE645/index.htm http://mos.stanford.edu/papers/ms_jssc_89.pdfhttp://www.ece.cmu.edu/~lowpower/cicc98.pdf
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