G. InterfaceTest PlanECE645 Project 2 Specification A. Names of the team member Nitin Raju B. Title of the project Floating point addition and multiplication according to ANSI/IEEE 754 C. Advantages of Floating Point Arithmetic It seems natural to use floating point arithmetic. Floating point arithmetic is easy to use and it comes closer to working the way we expect arithmetic to work than any other kind of arithmetic we can use in programs. The advantage of floating point is the wide range of numbers that it can represent and calculate with. It makes programming easier in that it relieves the programmer of the need to understand matters of scaling. D. Implemented arithmetic unit • Addition of 32 bit floating point numbers X+Y = Z (N=32) • Types and sizes of all operands Input A : std_logic_vector(31 downto 0) Input B : std_logic_vector(31 downto 0) Output C: std_logic_vector(31 downto 0) E. Real-life application of a given arithmetic unit General purpose microprocessors or digital signal processors make use of floating point arithmetic. Almost all signal processing algorithms are initially represented as double precision floating-point in languages such as Matlab. Also floating point arithmetic is used for matrix multiplication. It typically requires add and multiply floating-point units. F. Optimization criteria Due to the time-sensitive processing required in digital signal processors and microprocessors, the design is chosen to be optimized to reduce latency and to increase throughput. A pipelined architecture might be used to avoid the waste of computing cycle and lower the overall latency.G. Interface Input/Output interface with names, modes, types, and sizes of all ports Inputs: clk clock Input a, Input b input operands A and B Rounding rounding (00-round to nearest even, 01-round to zero, 10-round to +infinity, 11-round to –infinity) Floating_operation floating point operation (0 - Add, 1 - Int to float conversion, 2 - Float to int conversion)Outputs: output output infinity Asserted when output is the special value infinity inexact Asserted when the calculation is inexact, i.e. some accuracy has been lost during computation overflow Asserted when an overflow occurs, i.e. number is too large to be represented. underflow Asserted when an Underflow occurs, i.e. number is too small to be represented. zero Asserted when the output is a numeric zero snan Asserted when either operand is a SNAN qnan Output Asserted when output is a QNAN H. Software implementation used to generate test vectors Own implementation based on a public-domain arithmetic library. I. Test Plan I am planning to use C Language to generate test vectors and verify the results. At the moment the algorithm for generation of the test vector has not been decided but most probably random test vectors will be used. J. Language, Platform, and Tools • hardware description language: VHDL • platform: Xilinx FPGAs, Standard-cell ASIC based on the TSMC library • HW tools: Aldec Active-HDL + Synplicity Synplify Pro + Xilinx ISE for FPGA, ModelSim+ Synopsys Design Analyzer + Synopsys PrimeTime for ASIC’s. • SW tools: Visual
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