Mentor Graphics TutorialInitial SetupModelSim Start-upCreating/Editing VHDL FilesCompiling and Simulating VHDLMGC Software DocumentationMentor Graphics Tutorial This document is intended to assist ECE Students taking ECE-331, Digital Systems Design, ECE-332, Digital Design Lab, ECE-445, Computer Organization, and ECE-545, Introduction to VHDL, in setting up their computing environment for using Mentor Graphics tools on cpe02.gmu.edu. It also contains a basic tutorial for running VHDL simulations using the ModelSim software. The Mentor Graphics software is designed to operate in an X-terminal environment on unix workstations. MGC is currently installed on cpe02.gmu.edu. This means that MGC software can be accessed from the X-terminals in Room 133 of S&T-II as well as from other on/off-campus X-terminals (e.g., Linux ssh) or under MS-Windows using the X-windows emulator Cygnus XFree86 (via gmu ftp) . All MS-Windows machines available in the ECE Departmental Labs located in S&T II, rooms 203 and 265, as well as S&T I, rooms 2A and 2B have this X-terminal emulator installed on them. To start this terminal and connect to cpe02 simply click on the cpe02 icon visible on the desktop in the top-left corner of the screen. Please, keep in mind that an off-campus access over a dial-up connection is less than satisfactory in either environment, although suitable performance may be possible through a DSL or Cable-Modem connection. Initial Setup Specific Instructions for setting up your computing environment on cpe02.gmu.edu: 1. Log in to cpe02 using the username and password given to you in class. 2. Open the Workspace Menu by clicking with right mouse button anywhere on the desktop, go to the Tools menu and click on Terminal. The terminal window will open with the user@dab:path> prompt inside. The user part of the prompt shows your user name, and path - your current directory. 3. Prepare the "working" directory by typing initvsim at the prompt. This command will create the directory mgc_work and copy example files to this directory. Note: This step should only be performed once, otherwise your directory (and work) will be reinitialized.ModelSim Start-up You are now ready to start the ModelSim software and run a sample VHDL simulation. 1. At the prompt type cd mgc_work to change your working directory. Note: Always start ModelSim from this directory. Otherwise, the software may have difficulty finding and modifying files. 2. At the prompt type vsim & to start the ModelSim software. Note: The “&” causes the command to run in the background, keeping the UNIX prompt available for further commands. 3. Upon opening ModelSim for the first time, you will see a Welcome to ModelSim dialog box. (If this screen is not available, you can enable it by selecting Help > Enable Welcome from the Main window. It will then display the next time you start ModelSim.) By clicking the “Always open last project” radio button, you can skip this screen and proceed directly to your project. 4. To create a “Project” to organize all your laboratory work, click the “Create a Project” button.In the “Create a New Project” dialog box, select the “Create a new project from scratch” radio button, then click the “Browse” button to select the New Project’s Home. Simply click “OK” to create the new project directory in your “mgc_work” directory (where you started ModelSim).Next, type in ece332_labs (or other appropriate name) in the “New Project Name” box. Selecting OK causes the project directory to be created with a default working library. In the dialog box that asks if you want to create a new HDL source file for your project, click No. 5. Finally, to open your new project and begin work, select it from the pull-down menu arrow to the right of the “Open Project” button and text box. Then, click “Open Project” (or “Done”) in the Welcome to ModelSim dialog box. Now you are ready to begin editing your VHDL source code and compiling your project for simulation.Creating/Editing VHDL Files There are several ways to create/edit VHDL source files prior to compilation and simulation: • Use the Notepad editor from within ModelSim • Create the files outside of ModelSim and “Import” them into your project • Use a UNIX editor like vi, emacs, or pico • Use an external text editor and upload/download the files to cpe02 For this part of the tutorial, use one of these methods to create the VHDL files or3.vhd and or3_testbench.vhd: or3.vhd --------------------------------------------------------------- -- Author : Dr. Ron Hayne -- Date : April 13, 2003 -- Course : ECE332 -- File Name : or3.vhd -- Design Units : OR3 -- Purpose of Code : This is an example circuit provided for -- the Mentor Graphics Tutorial. -- Hardware modeled : Behavioral model of a 3-input OR gate. -- Model Limits : None known -- Known Errors : None known -- Design Library : work -- Dependencies : None -- Environment: -- Simulator : Mentor Graphics (ModelSim) V5.4d -- Platform : Unix (SunOS 5.8) -- -- Change List (most recent on top) -- Date Who What -- ------- --- ---- -- 07Jun03 rjh Update to ESA coding stds -- 13Apr03 rjh Creation ---------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity OR3 is port( A : in std_logic; B : in std_logic; C : in std_logic; Z : out std_logic ); end OR3;--------------------------------------------- architecture BEHAVE of OR3 is begin Z <= A or B or C after 10 ns; end BEHAVE; or3_test_bench.vhd --------------------------------------------------------------- -- Author : Dr. Ron Hayne -- Date : May 26, 2003 -- Course : ECE332 -- File Name : or3_testbench.vhd -- Design Units : OR3_Testbench -- Purpose of Code : This is a top level testbench for the OR3 -- example which is provided for the Mentor -- Graphics Tutorial. -- Hardware modeled : This testbench creates an instance of the -- OR3 circuit and then drives the inputs -- and checks the results. -- Model Limits : VHDL-93 Syntax (report) -- Known Errors : None known -- Design Library : work -- Dependencies