[7] Smith, John W., “The Scientist and Engineer's Guide to DECE645 PROJECT 2 Specifications A. Names of the Team Members Joe Czarnaski B. Title of the project 64-bit Signed Multiplier Accumulator used for Digital Filter Applications in the PASTA Remote Sensor Platform C. Introduction Digital Filters are used in a wide variety of signal processing applications such as image processing, speech compression, music signal processing, radar signal processing, and adaptive signal processing techniques. Most Digital Signal Processing (DSP) functions typically use a multiply-accumulate (MAC) instruction in which two operands are multiplied together and the result is added to the contents of an accumulator. In some cases the results are scaled and rounded off and then written back to the accumulator. The motivation for this project is to create a hardware and software implementation of this MAC function which can then be incorporated into a general purpose DSP application for the PASTA Remote Sensor Platform [1]. D. Implemented arithmetic unit 1. Function: This project implements a 64-bit signed multiplier-accumulator (MAC) accumulating at least 256 partial products 2. Formulas Describing the Units Operation: ∑==2561*iiiBAS 3. Types and Sizes Of All Operands: Inputs (X, Y) : std_logic_vector (63 downto 0), 64-bit input operand Output (S) : std_logic_vector (135 downto 0), 136-bit output result *Note: 64-bit input multiplication produces a 128-bit result. The number of bits in the result S of executing a multi-operand addition is given by the equation:⎡⎤nk2log+ for this project, S = = 128 + 8 = 136 bits ⎡256log1282+⎤ 4. Control Signals: The control signals include: CLK: input clock CE: input clock enable ENA: input enable for input and output registers RST: input control pin for reset FD: input pin to identify the first pair of operands A and B. RDY: output pin indicating completion of N summations COUT: carry output bit E. Real-life application of a given arithmetic unit There are many different types of DSP functions available to designers. Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, Fast Fourier Transforms (FFT) and mixers are just a few that make use of multiply-accumulate functions along with addition and subtraction functions. This project will focus MAC operations which are used in FIR filters due its wide spread use as the primary type of filter used in Digital Signal Processing F. Optimization criteria This design will be optimized to minimize latency since most applications that require DSP are real-time applications on high frequency signals. However, since other applications under investigation such as low frequency seismic sensors or low frequency acoustics, a trade off can be made to allow higher latency to reduce area and power. The amount of power expended per operation is a critical factor for remote systems which rely on a limited battery supply.G. Interface H. Software implementation used to generate test vectors Software will include a custom implementation for the MAC function as well as public-domain software which will be used to generate input coefficients of an FIR filter. I. Test plan An input digitized data file will be supplied containing acoustic, seismic, or other sensor data which will then be executed using a test C program incorporating the MAC function. The results can then be used for an input vector file which can be read by a testbench for the digital filter hardware implementation. The results will be compared to verify functionality. Area, delay, throughput, latency can be analyzed using Synplify and Synopsys tools for the appropriate target FPGA and ASIC respectively. J. Language, Platform, and Tools 1. Hardware Description Language: VHDL-93 2. Platforms: • FPGA – Xilinx XC2V3000FG676C, chip used in the PASTA FPGA module • ASIC – custom ASICs based on the 90 nm TCBN90G TSMC library of standard cells 3. Hardware Tools:A. Initial VHDL Development: • SW: Mentor Graphics ModelSim SE Plus v. 5.7e • HW: IBM Think Pad Intel® Pentium® M Processor, 1700 MHz, 1.69 GHz, 512, MB of RAM, Microsoft Windows XP Pro, Service Pack-1 B. FPGA Final Development: • SW: Aldec Active-HDL v6.2, Synplicity Synplify Pro v7.3, and Xilinx ISE for FPGAs v6.2i • HW: Dell Workstation, Intel® Pentium® Processor, running Microsoft Windows, in FPGA LAB ST2 Room 203 C. ASIC Final Development: • SW: Mentor Graphics ModelSim v. 5.4d, Synopsys Design Analyzer v-2003.12-SP1 Feb. 13, 2004, Synopsys PrimeTime v-2004.06-SP1 Aug. 23, 2004 • HW: Sun Workstation, Solaris 5.8, cpe02.gmu.edu 4. Software Tools: Coefficients for FIR filter implementations will be generated using Systolix FilterExpress v5.1 freeware utility for digital filter design. This utility can be used for the analysis of several types of FIR and IIR filter transfer functions. C code development will be done using GCC compiler V3.2.3 on Linux Workstation: Dell Precision Workstation Model 330 • Pentium 4, 1.4 GHz, i850 chipset (Tehama) • Hard Drive: Western Digital WD1200BB 120 GB • Video Card: nVidia RIVA TNT2 • Floppy Drive • CD ROM Drives: CDR-8482B, Sony, CD-RW CRX160X • OS: RedHat Linux 9-Kernel 2.4.20-8K. List of references [1] Power Aware Sensing Tracking and Analysis. http://pasta.east.isi.edu/ [2] Application Note AN9603.2, “An Introduction To Digital Filters” – Intersil TM [3] Olay, Rufino, “FIR Filter Implementation”, Quick Logic TM Application Note [4] Parhami, Behrooz, “Computer Arithmetic Algorithms and Hardware Designs”, Oxford University Press, New York, New York, 2000 [5] Hands, Gordon, “High-Performance DSP Capability Within an Optimized Low-Cost FPGA Architecture”, FPGA and Programmable Logic Journal, July 6, 2004, Available: http://www.fpgajournal.com/articles/20040706_lattice.htm [6] Pickerd, John, "Impulse-Response Testing Lets a Single Test Do the Work of Thousands," EDN, April 27, 1995. [7] Smith, John W., “The Scientist and Engineer's Guide to Digital Signal Processing", California Technical Publishing, December 27, 2001. Available: http://www.dspguide.com/pdfbook.htm [8] Quinnell, Richard A., “Designing Digital Filters”, TechOnLine, August 1, 2003. Available: http://www.techonline.com/community/ed_resource/feature_article/26649 [9] Xilinx Vertex II selection guide,