REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.aAD5220One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 © Analog Devices, Inc., 1998Increment/DecrementDigital PotentiometerFUNCTIONAL BLOCK DIAGRAMUP/DOWNCNTRRSDECODE740HPORENAD5220VDDAWBGNDCLKCSU/DFEATURES128 PositionPotentiometer Replacement10 k⍀, 50 k⍀, 100 k⍀Very Low Power: 40 ␮A MaxIncrement/Decrement Count ControlAPPLICATIONSMechanical Potentiometer ReplacementRemote Incremental Adjustment ApplicationsInstrumentation: Gain, Offset AdjustmentProgrammable Voltage-to-Current ConversionProgrammable Filters, Delays, Time ConstantsLine Impedance MatchingPower Supply AdjustmentGENERAL DESCRIPTIONThe AD5220 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performsthe same electronic adjustment function as a potentiometer orvariable resistor. These products were optimized for instrumentand test equipment push-button applications. A choice betweenbandwidth or power dissipation are available as a result of thewide selection of end-to-end terminal resistance values.The AD5220 contains a fixed resistor with a wiper contact thattaps the fixed resistor value at a point determined by a digitallycontrolled UP/DOWN counter. The resistance between thewiper and either end point of the fixed resistor provides a con-stant resistance step size that is equal to the end-to-end resis-tance divided by the number of positions (e.g., RSTEP = 10 kΩ/128 = 78 Ω). The variable resistor offers a true adjustable valueof resistance, between the A terminal and the wiper, or the Bterminal and the wiper. The fixed A-to-B terminal resistance of10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficientof 800 ppm/°C.The chip select CS, count CLK and U/D direction controlinputs set the variable resistor position. These inputs that con-trol the internal UP/DOWN counter can be easily generatedwith mechanical or push button switches (or other contact closuredevices). External debounce circuitry is required for the nega-tive-edge sensitive CLK pin. This simple digital interface elimi-nates the need for microcontrollers in front panel interface designs.The AD5220 is available in both surface mount (SO-8) and the8-lead plastic DIP package. For ultracompact solutions selectedmodels are available in the thin µSOIC package. All parts areguaranteed to operate over the extended industrial temperaturerange of –40°C to +85°C. For 3-wire, SPI compatible inter-face applications, see the AD7376/AD8400/AD8402/AD8403products.UPCOUNT DETAILVDD = 5.5VVA = 5.5VVB = 0Vf = 100kHzCLKVWB50mV/DIV5V/DIVFigure 2a. Stair-Step Increment Output VDD = 5.5VVA = 5.5VVB = 0Vf = 60kHzCOUNT00H v 3FH v 00HVWRfCLK = 60kHzFigure 2b. Full-Scale Up/Down CountAD5220CSU/DCLK+5VUP/DOWNINCREMENTFigure 1. Typical Push-Button Control Application–2–REV. 0AD5220–SPECIFICATIONSELECTRICAL CHARACTERISTICSParameter Symbol Conditions Min Typ1Max UnitsDC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRsResistor Differential NL2R-DNL RWB, VA = NC, RAB = 10 kΩ –1 ±0.4 +1 LSBRWB, VA = NC, RAB = 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSBResistor Nonlinearity2R-INL RWB, VA = NC, RAB = 10 kΩ –1 ±0.5 +1 LSBRWB, VA = NC, RAB = 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSBNominal Resistor Tolerance ∆RTA = +25°C –30 +30 %Resistance Temperature Coefficient ∆RAB/∆TVAB = VDD, Wiper = No Connect 800 ppm/°CWiper Resistance RWIW = VDD/R, VDD = +3 V or +5 V 40 100 ΩDC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRsResolution N 7 BitsIntegral Nonlinearity3INL RAB = 10 kΩ –1 ±0.5 +1 LSBRAB = 50 kΩ, 100 kΩ –0.5 ±0.2 +0.5 LSBDifferential Nonlinearity Error3DNL RAB = 10 kΩ –1 ±0.4 +1 LSBRAB = 50 kΩ, 100 kΩ –0.5 ±0.1 +0.5 LSBVoltage Divider Temperature Coefficient ∆VW/∆T Code = 40H20 ppm/°CFull-Scale Error VWFSECode = 7FH–2 –0.5 0 LSBZero-Scale Error VWZSECode = 00H0 +0.5 +1 LSBRESISTOR TERMINALSVoltage Range4VA, VB, VW0VDDVCapacitance5 A, B CA, CBf = 1 MHz, Measured to GND, Code = 40H10 pFCapacitance5 WCWf = 1 MHz, Measured to GND, Code = 40H48 pFCommon-Mode Leakage ICMVA = VB = VW7.5 nADIGITAL INPUTS AND OUTPUTSInput Logic High VIHVDD = +5 V/+3 V 2.4/2.1 VInput Logic Low VILVDD = +5 V/+3 V 0.8/0.6 VInput Current IILVIN = 0 V or +5 V ±1 µAInput Capacitance5CIL5pFPOWER SUPPLIESPower Supply Range VDD2.7 5.5 VSupply Current IDDVIH = +5 V or VIL = 0 V, VDD = +5 V 15 40 µAPower Dissipation6PDISSVIH = +5 V or VIL = 0 V, VDD = +5 V 75 200 µWPower Supply Sensitivity PSS 0.004 0.015 %/%DYNAMIC CHARACTERISTICS5, 7, 8Bandwidth –3 dB BW_10K RAB = 10 kΩ, Code = 40H650 kHzBW_50K RAB = 50 kΩ, Code = 40H142 kHzBW_100K RAB = 100 kΩ, Code = 40H69 kHzTotal Harmonic Distortion THDWVA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz 0.002 %VW Settling Time tSVA = VDD, VB = 0 V, 50% of Final Value,10K/50K/100K 0.6/3/6 µsResistor Noise Voltage eNWBRWB = 5 kΩ, f = 1 kHz 14 nV/√HzINTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9Input Clock Pulsewidth tCH, tCLClock Level High or Low 25 nsCS to CLK Setup Time tCSS20 nsCS Rise to Clock Hold Time tCSH20 nsU/D to Clock Fall Setup Time tUDS10 nsNOTES1Typicals represent average readings at +25°C and VDD = +5 V.2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiperpositions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.4Resistor terminals A, B, W have no limitations on polarity with respect to each other.5Guaranteed by design and not subject to production test.6PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.7Bandwidth, noise