1®CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143| Intersil (and design) is a registered trademark of Intersil Americas Inc.Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2003, 2004. All Rights ReservedAll other trademarks mentioned are the property of their respective owners.8-Bit, CMOS R2R D/A ConverterThe HI3338 family are CMOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce “rail-to-rail” output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground.The data complement control allows the inversion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, “glitch” energy has been kept very low by segmenting and thermometer encoding of the upper 3 bits.The HI3338 is manufactured to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance.Features• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .100mW • R2R Output, Segmented for Low “Glitch”• CMOS/TTL Compatible Inputs• Fast Settling (Typ) . . . . . . . . . . . . . . . . . . 20ns to 1/2 LSB• Feedthrough Latch for Clocked or Unclocked Use• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB• Data Complement Control• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . . 50MHz• Unipolar or Bipolar Operation• Linearity (INL)- HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.75 LSB• Pb-free AvailableApplications• TV/Video Display• High Speed Oscilloscope Display• Digital Waveform Generator• Direct Digital Frequency Synthesis• Wireless CommunicationPinoutHI3338 (SOIC)TOP VIEWOrdering InformationPART NUMBERTEMP. RANGE (°C) PACKAGEPKG. DWG. #HI3338KIB -40 to 85 16 Ld SOIC M16.3HI3338KIBZ (Note)-40 to 85 16 Ld SOIC (Pb-free)M16.3NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.14151691312111012345768D7D6D5D4D3D2VSSD1VDDCOMPVREF+VOUTVREF-VEED0LEFN4134.3HI3338Data Sheet July 20042Functional DiagramDie CharacteristicsDIE DIMENSIONS:2,740µm x 3,310µm x 530 ±50µmMETALLIZATION:Type: Al with 0.8% SiThickness: 11kÅ ±1kÅGLASSIVATION:Type: 3% PSGThickness: 13kÅ ±2.6kÅCOMPTO 7-LINEVDDD7D6D5D4D3D2D1D0VSS161514123456798THERMOMETERENCODER3-BITLEVELSHIFTERSFEEDTHROUGHLATCHES8R4R2R2R2R2R2R2R8R8R8R4R1310VEEVREF-VOUTVREF+12112RRRRLER ≅ 160ΩRRRRHI33383Absolute Maximum Ratings Thermal InformationDC Supply-Voltage Range. . . . . . . . . . . . . . . . . . . . . . .-0.5V to +8V(VDD - VSS or VDD - VEE, Whichever Is Greater)Input Voltage RangeDigital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5VAnalog Pins (VREF+, VREF-, VOUT) . . . .VDD - 8V to VDD + 0.5VDC Input CurrentDigital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . ±20mARecommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5VOperating ConditionsHI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oCThermal Resistance (Typical) θJA (oC/W)SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oCMaximum Storage Temperature Range, TSTG . . . . -65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC(Lead Tips Only)CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE clocked at 20MHz, RL ≥ 1MΩ,Unless Otherwise SpecifiedPARAMETER TEST CONDITIONS MIN TYP MAX UNITSACCURACYResolution 8 - - BitsIntegral Linearity Error See Figure 4 - - ±0.75 LSBDifferential Linearity Error See Figure 4 - - ±0.5 LSBGain Error Input Code = FFHEX, See Figure 3 - - ±0.5 LSBOffset Error Input Code = 00HEX, See Figure 3 - - ±0.25 LSBDIGITAL INPUT TIMINGUpdate Rate To Maintain 1/2 LSB Settling DC 50 - MHzUpdate Rate VREF- = VEE = -2.5V, VREF+ = +2.5V DC 20 - MHzSet Up Time tSU1For Low Glitch - -2 - nsSet Up Time tSU2For Data Store - 8 - nsHold Time tHFor Data Store - 5 - nsLatch Pulse Width tWFor Data Store - 5 - nsLatch Pulse Width tWVREF- = VEE = -2.5V, VREF+ = +2.5V - 25 - nsOUTPUT PARAMETERS RL Adjusted for 1VP-P OutputOutput Delay tD1From LE Edge - 25 - nsOutput Delay tD2From Data Changing - 22 - nsRise Time tr10% to 90% of Output - 4 - nsSettling Time tS10% to Settling to 1/2 LSB - 20 - nsOutput Impedance VREF+ = 6V, VDD = 6V 120 160 200 ΩGlitch Area - 150 - pV-sGlitch Area VREF- = VEE = -2.5V, VREF+ = +2.5V - 250 - pV-sREFERENCE VOLTAGEVREF+ Range (+) Full Scale (Note 1) VREF- + 3 - VDDVVREF- Range (-) Full Scale (Note 1) VEE -VREF+ - 3 VVREF+ Input Current VREF+ = 6V, VDD = 6V - 40 50 mAHI33384SUPPLY VOLTAGEStatic IDD or IEELE = Low, D0 - D7 = High - 100 220 µALE = Low, D0 - D7 = Low - - 100 µADynamic IDD or IEEVOUT = 10MHz, 0V to 5V Square Wave - 20 - mADynamic IDD or IEEVOUT = 10MHz, ±2.5V Square Wave - 25 - mAVDD Rejection 50kHz Sine Wave Applied - 3 - mV/VVEE Rejection 50kHz Sine Wave Applied - 1 - mV/VDIGITAL INPUTS D0 - D7, LE, COMPHigh Level Input Voltage Note 1 2 - - VLow Level Input Voltage Note 1 - - 0.8 VLeakage Current - ±1 ±5 µACapacitance - 5 - pFTEMPERATURE COEFFICIENTSOutput Impedance - 200 - ppm/×oCNOTE:1. Parameter not tested, but guaranteed by design or characterization.Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE clocked at 20MHz, RL ≥ 1MΩ,Unless Otherwise Specified (Continued)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTiming DiagramsFIGURE 1. DATA TO LATCH ENABLE TIMING FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT