ContentsPin Configuration GAL16V8 Ordering Information DC Electrical Characteristics AC Switching CharacteristicsGAL16V8High Performance E2CMOS PLDGeneric Array Logic™1220I/CLKIIIIIIII GNDVccI/O/Q I/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/OE468911 131416181101120I/CLKIIIIIIIIGNDVccI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/OE515PLCCGAL16V8DIPGAL16V8Top ViewI/CLKII/O/QII/O/QII/O/QII/O/QII/O/QII/O/QII/O/QII/O/QCLK88888888OEOLMCOLMCOLMCOLMCOLMCOLMCOLMCOLMCPROGRAMMABLEAND-ARRAY(64 X 32) I/OECopyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subjectto change without notice.LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com16v8_09Features• HIGH PERFORMANCE E2CMOS® TECHNOLOGY— 3.5 ns Maximum Propagation Delay— Fmax = 250 MHz— 3.0 ns Maximum from Clock Input to Data Output— UltraMOS® Advanced CMOS Technology• 50% to 75% REDUCTION IN POWER FROM BIPOLAR— 75mA Typ Icc on Low Power Device— 45mA Typ Icc on Quarter Power Device• ACTIVE PULL-UPS ON ALL PINS•E2 CELL TECHNOLOGY— Reconfigurable Logic— Reprogrammable Cells— 100% Tested/100% Yields— High Speed Electrical Erasure (<100ms)— 20 Year Data Retention• EIGHT OUTPUT LOGIC MACROCELLS— Maximum Flexibility for Complex Logic Designs— Programmable Output Polarity— Also Emulates 20-pin PAL® Devices with FullFunction/Fuse Map/Parametric Compatibility• PRELOAD AND POWER-ON RESET OF ALL REGISTERS— 100% Functional Testability• APPLICATIONS INCLUDE:— DMA Control— State Machine Control— High Speed Graphics Processing— Standard Logic Speed Upgrade• ELECTRONIC SIGNATURE FOR IDENTIFICATION• LEAD-FREE PACKAGE OPTIONSDescriptionThe GAL16V8, at 3.5 ns maximum propagation delay time, com-bines a high performance CMOS process with Electrically Eras-able (E2) floating gate technology to provide the highest speedperformance available in the PLD market. High speed erase times(<100ms) allow the devices to be reprogrammed quickly and ef-ficiently.The generic architecture provides maximum design flexibility byallowing the Output Logic Macrocell (OLMC) to be configured bythe user. An important subset of the many architecture configura-tions possible with the GAL16V8 are the PAL architectures listedin the table of the macrocell description section. GAL16V8 devicesare capable of emulating any of these PAL architectures with fullfunction/fuse map/parametric compatibility.Unique test circuitry and reprogrammable cells allow complete AC,DC, and functional testing during manufacture. As a result, LatticeSemiconductor delivers 100% field programmability and function-ality of all GAL products. In addition, 100 erase/write cycles anddata retention in excess of 20 years are specified.Functional Block DiagramPin Configuration1101120I/CLKIIIIIIIIGNDVccI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/OE515SOICGAL16V8TopViewLead-FreePackageOptionsAvailable!Specifications GAL16V82)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP5.35.20.3511JL3-D8V61LAGCCLPdaeL-02534 5118V61LAG5-DJLCCLPdaeL-025.7751518V61LAG7-DLPPIDcitsalPniP-021518V61LAG7-DJLCCLPdaeL-021518V61LAG7-DLS -02niPCIOS0101755PQ01-D8V61LAGPIDcitsalPniP-0255JQ01-D8V61LAGCCLPdaeL-025118V61LAG01-DPLPIDcitsalPniP-025118V61LAG01-DJLCCLPdaeL-025118V61LAG01-DLS niP-02CIOS51210155PQ51-D8V61LAGPIDcitsalPniP-0255JQ51-D8V61LAGCCLPdaeL-0209PL51-D8V61LAGPIDcitsalPniP-0209L51-D8V61LAGJ daeL-02CCLP09L51-D8V61LAGSCIOSniP-0252512155PQ52-D8V61LAGPIDcitsalPniP-0255JQ52-D8V61LAGCCLPdaeL-0209PL52-D8V61LAGPIDcitsalPniP-0209L52-D8V61LAGJCCLPdaeL-0209L52-D8V61LAGS -02niPCIOS)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP5.7750318V61LAG7-DIPLPIDcitsalPniP-020318V61LAG7-DIJLCCLPdaeL-0201017 0318V61LAG01-DIPLPIDcitsalPniP-020318V61LAG01-DIJLCCLPdaeL-02512101031IPL51-D8V61LAGPIDcitsalPniP-02031IJL51-D8V61LAGCCLPdaeL-0202311156IPQ02-D8V61LAGPIDcitsalPniP-0256IJQ02-D8V61LAGCCLPdaeL-0252512156IPQ52-D8V61LAGPIDcitsalPniP-0256IJQ52-D8V61LAGCCLPdaeL-02031IPL52-D8V61LAGPIDcitsalPniP-02031IJL52-D8V61LAGCCLPdaeL-02Industrial Grade SpecificationsGAL16V8 Ordering InformationConventional PackagingCommercial Grade SpecificationsSpecifications GAL16V83Part Number DescriptionBlank = CommercialI = IndustrialGradePackagePowerL = Low PowerQ = Quarter PowerSpeed (ns)XXXXXXXX XX X XX XDevice Name_P = Plastic DIPPN = Lead-free Plastic DIPJ = PLCCJN = Lead-free PLCCS = SOICGAL16V8DLead-Free PackagingCommercial Grade Specifications)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP5.35.20.3511NJL3-D8V61LAGCCLPdaeL-02eerF-daeL534 5118V61LAG5-DJLNeerF-daeLCCLPdaeL-025.7751518V61LAG7-DLNPeerF-daeLPIDcitsalPniP-021518V61LAG7-DJLNeerF-daeLCCLPdaeL-020101755NPQ01-D8V61LAGPIDcitsalPniP-02eerF-daeL55NJQ01-D8V61LAGCCLPdaeL-02eerF-daeL5118V61LAG01-DPLNeerF-daeLPIDcitsalPniP-025118V61LAG01-DJLNeerF-daeLCCLPdaeL-0251210155PQ51-D8V61LAGNeerF-daeLPIDcitsalPniP-0255JQ51-D8V61LAGNeerF-daeLCCLPdaeL-0209PL51-D8V61LAGNeerF-daeLPIDcitsalPniP-0209L51-D8V61LAGNJeerF-daeLdaeL-02CCLP52512155PQ52-D8V61LAGNeerF-daeLPIDcitsalPniP-0255JQ52-D8V61LAGNeerF-daeLCCLPdaeL-0209PL52-D8V61LAGNeerF-daeLPIDcitsalPniP-0209L52-D8V61LAGNJeerF-daeLCCLPdaeL-02Specifications GAL16V84The following discussion pertains to configuring the output logicmacrocell. It should be noted that actual implementation is accom-plished by development software/hardware and is completely trans-parent to the user.There are three global OLMC configuration modes possible:simple, complex, and registered. Details of each of these modesare illustrated in the following pages. Two global bits, SYN andAC0, control the mode configuration for all macrocells. The XORbit of each macrocell controls the polarity of the output in any of thethree modes, while the AC1 bit of each of the macrocells controlsthe input/output configuration. These two global and 16 individ-ual architecture bits define all possible configurations in a GAL16V8. The information given on these architecture bits is only to givea better understanding of the device. Compiler software will trans-parently set these architecture bits from the pin definitions, so theuser should not need to directly manipulate these architecture bits.The following is a list of the PAL architectures that the GAL16V8can emulate. It also shows the OLMC mode under which theGAL16V8 emulates