Department of Electrical Engineering - SystemsEE 459L - Embedded Systems Design LaboratoryThe 74ACT715 Video Sync Generatorby Allan G. WeberFall 2006The 74ACT715 video sync generator is used to generate the necessar y synchronization signals to pro ducea video signal. In most cases the compos ite sync from the sync generato r is combined with a video signalfrom other circuitry to produce a compos ite video signal.InitializationWhen power e d up the 74ACT715 is configured to run at rates compatible with RS-170 video but the internalclock in the chip must be enabled for it to start outputting sync signals. To enable the clock, bit 10 in thestatus register must be changed from a zero to a one. If no other registers in the chip have to be alteredthis can be done from a microcontroller by hardwiring the proper settings on the eight data input lines andthen performing clear and load operations. The circ uit show below (copied from Figures 6 in 74ACT715datasheet) s hows how this is done.D0 D1 D2 D3 D4 D5 D6 D7 CLR GNDVCC ADDR/DATA L/HBYTE LOAD ODD/EVEN HSYNVDR VCSYNC HBLHDR VCBLANK CLOCK1 2 3 4 5 6 7 8 9 1020 19 18 17 16 15 14 13 12 11+5v+5v+5v+5vClear InputLoad InputClock Input74ACT715CLEARLOADTimeFigure 1: Initializing the 74ACT715 for RS-170 VideoThis circuit requires two input signals (CLEAR and LOAD) in addition to the clock signal. The CLEARline is pulsed from low to high to low to reset the device. After that the LOAD line is pulsed from highto low to high. TheADDR/DATA line is in the high state to indicate that data is being loaded, and theL/HBYTE is in the high state to cause the data to be loaded into the upper byte of the status register.With D2 of the data lines held high and the others low, this s e ts bit 10 in the status register to a one andenables the clo ck. Once these operations are done, the chip will start outputing RS-170 sync signals on thefive output lines.Output SignalsThere are five output signals that come out of the 74ACT715 . Pin 16 is used to indicate whether thevideo is in the odd or even field of the frame. The other four are for various sync signals and internally the74ACT715 generates ten different sync signals tha t can appear on these pins.EE 459L, Rev. 11/7/06 1HBLANK Horizontal blankingVBLANK Vertical blankingCBLANK Composite blanking (ANDing of HBLANK and VBLANK)HSYNC Horizontal syncVSYNC Vertical syncCSYNC Composite sync (ANDing of HSYNC and VSYNC)HGATE Horizontal gating (or horizontal drive)VGATE Vertical gating (or vertical drive)CURSOR Cursor positionVINT Vertical interruptSince there are only four output pins for the sync signals only four of the above signals can actua lly beoutput at any one time. The states of bits 0, 1 and 2 in the status register determine which signals willappear on the four output pins. For the defa ult se ttings the following fo ur are output:Pin Number Pin Na me Signal Name Signa l DescriptionPin 12 VCBLANK CBLANK Composite blankingPin 13 HBLHDR HGATE Horizontal gate (horzontal drive)Pin 14 VCSYNC CSYNC Composite syncPin 15 HSYNVDR VGATE Vertical ga te (vertical drive)If a different set of sync signals is required, refer to the datasheet to see if bits 0, 1 and 2 in the statusregister can be set differently to get the desired signals on the four output lines.Vertical Timing SignalsThe diagrams on page 3 show the vertical time signals for both an odd and an even field. The vertical gatingsignal (VGATE) goe s low at the beginning of vertical bla nk ing and stays low for ten hor izontal line times(635µsec). Vertical blanking stays low for twenty lines times (1271µsec). Note that the horizontal gatingor horizontal drive signal (HGATE) is a consistent pulse train that give one equal le ngth pulse for eachhorizontal line line. When counting vertical lines, this signal may work better than CSYNC since it doesnot have the serration and equalization pulses during the vertical blanking period.Horizontal Timing SignalsThe diagrams on page 4 show the horizontal timing signals. VCBLANK (composite blanking) is low for10.9µsec during the blanking period of each horizontal line. The rest of the 63.5µsec line time is for active(viewable) video. The blanking period consists of a 1.5µsec front porch before the sync signal, a 4.7µsecsync period, and a 4.7µsec back porch after the sync signal. VCSYNC (composite sync) will be low duringthe sync period. The horiz ontal gating signal (HGATE) that appears on the HBL HDR output goes low atthe start of the blanking period and r e tur ns high at the end of the sync period.EE 459L, Rev. 11/7/06 21 2121 212Field 1Field 21 2 3 4 5 6 7 8 9 10 2111 22 23262261Field 2Field 11 2 3 4 5 6 7 8 9 10 2120 22 23263262. . .. . .. . .. . .Vertical Timing SignalsPin 14 VCSYNC = Composite Sync (CSYNC)Pin 14 VCSYNC = Composite Sync (CSYNC)Pin 12 VCBLANK = Composite Blanking (CBLANK)Pin 15 HSYNDRV = Vertical Gating (VGATE)Pin 12 VCBLANK = Composite Blanking (CBLANK)74ACT715 Timing Signals in RS-170 ModePin 13 HBLHDR = Horizontal Gating (HGATE)Pin 13 HBLHDR = Horizontal Gating (HGATE)Pin 15 Odd/Even = Field IndicatorPin 15 Odd/Even = Field IndicatorPin 15 HSYNDRV = Vertical Gating (VGATE). . .. . .Blanking(10.9µsec)Active Video(52.6µsec)Video Line(63.5µsec)Pin 14 VCSYNC = Composite Sync (CSYNC)Pin 13 HBLHDR = Horizontial Gating (HGATE)Horizontal Timing SignalsPin 12 VCBLANK = Composite Blanking
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