HM628128D Series1 M SRAM (128-kword × 8-bit)ADE-203-996 (Z)Preliminary, Rev. 0.0Jan. 20, 1999DescriptionThe Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128DSeries has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. The HM628128D Series offers low power standby power dissipation;therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.Features• Single 5 V supply: 5 V ± 10%• Access time: 55 ns/70 ns (max)• Power dissipation Active: 30 mW/MHz (typ) Standby: 10 µW (typ)• Completely static memory. No clock or timing strobe required• Equal access and cycle times• Common data input and output Three state output• Directly TTL compatible all inputs• Battery backup operation 2 chip selection for battery backupHM628128D Series2Ordering InformationType No. Access time PackageHM628128DLP-5HM628128DLP-755 ns70 ns600-mil 32-pin plastic DIP (DP-32)HM628128DLP-5SLHM628128DLP-7SL55 ns70 nsHM628128DLP-5ULHM628128DLP-7UL55 ns70 nsHM628128DLFP-5HM628128DLFP-755 ns70 ns525-mil 32-pin plastic SOP (FP-32D)HM628128DLFP-5SLHM628128DLFP-7SL55 ns70 nsHM628128DLFP-5ULHM628128DLFP-7UL55 ns70 nsHM628128DLTS-5HM628128DLTS-755 ns70 ns8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC)HM628128DLTS-5SLHM628128DLTS-7SL55 ns70 nsHM628128DLTS-5ULHM628128DLTS-7UL55 ns70 nsHM628128DLT-5HM628128DLT-755 ns70 nsNormal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D)HM628128DLT-5SLHM628128DLT-7SL55 ns70 nsHM628128DLT-5ULHM628128DLT-7UL55 ns70 nsHM628128DLR-5HM628128DLR-755 ns70 nsReverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR)HM628128DLR-5SLHM628128DLR-7SL55 ns70 nsHM628128DLR-5ULHM628128DLR-7UL55 ns70 nsHM628128D Series3Pin Arrangement1234567891011121314151632313029282726252423222120191817A11 A9 A8A13 WECS2A15 VCC NCA16 A14A12 A7 A6 A5 A4OEA10CS1I/O7I/O6I/O5I/O4I/O3VSSI/O2I/O1I/O0A0A1A2A3(Top view)32-pin TSOP (Normal Type TSOP)32-pin DIP/SOP3231302928272625242322212019181712345678910111213141516 OE A10 CS1 I/O8I/O7I/O6I/O5 I/O4 VSSI/O3I/O2 I/O1A0 A1 A2A3A11A9A8A13WECS2A15VCCNCA16A14A12A7A6A5A432-pin TSOP (Reverse Type TSOP)(Top View)1234567891011121314151632313029282726252423222120191817NCA16A14A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0I/O1I/O2 VSSVCCA15CS2WEA13A8A9A11OEA10CS1I/O7I/O6I/O5I/O4I/O3(Top view)Pin DescriptionPin name FunctionA0 to A16 Address inputI/O0 to I/O7 Data input/outputCS1 Chip select 1CS2 Chip select 2WE Write enableOE Output enableVCCPower supplyVSSGroundNC No connectionHM628128D Series4Block Diagram•••••••••••I/O0I/O7WEOEA14 A16 A15 A8 A11VCCVSS RowdecoderMemory matrix 512 x 2,048Column I/OColumn decoderInputdatacontrolTiming pulse generatorRead/Write controlA9A12A7A6A5A4A3A2A1A0A10A13 MSBLSBMSBLSBCS1CS2HM628128D Series5Operation TableCS1 CS2 WE OE I/O OperationHH××High-Z StandbyLL××High-Z StandbyLL××High-Z StandbyL H H L Dout Read L H L H Din WriteL H L L Din WriteL H H H High-Z Output disableNote: H: VIH, L: VIL, ×: VIH or VILAbsolute Maximum RatingsParameter Symbol Value UnitPower supply voltage relative to VSSVCC–0.5 to +7.0 VTerminal voltage on any pin relative to VSSVT–0.5*1 to VCC + 0.3*2VPower dissipation PT1.0 WStorage temperature range Tstg –55 to +125 °CStorage temperature range under bias Tbias –20 to +85 °CNotes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns2. Maximum voltage is +7.0 VDC Operating ConditionsParameter Symbol Min Typ Max Unit NoteSupply voltage VCC4.5 5.0 5.5 VVSS000VInput high voltage VIH2.2 — VCC + 0.3 VInput low voltage VIL–0.3 — 0.8 V 1Ambient temperature range Ta –20 — +70 °CNote: 1. VIL min: –1.5 V for pulse half-width ≤ 30 nsHM628128D Series6DC CharacteristicsParameter Symbol Min Typ*1Max Unit Test conditionsInput leakage current |ILI| ——1 µA Vin = VSS to VCCOutput leakage current |ILO| ——1 µACS1 = VIH or CS2 = VIL orOE = VIH or WE = VIL, VI/O = VSS to VCCOperating current ICC——15mACS1 = VIL, CS2 = VIH,others = VIH/VIL, II/O = 0 mAAverage operating current ICC1— — 60 mA Min cycle, duty = 100%II/O = 0 mA, CS1 = VIL, CS2= VIH, Others = VIH/VILICC2— 6 20 mA Cycle time = 1 µs,duty = 100%,II/O = 0 mA, CS1 ≤ 0.2 V,CS2 ≥ VCC – 0.2 V,VIH ≥ VCC – 0.2 V,VIL ≤ 0.2 VStandby current ISB— — 2 mA (1) CS1 = VIH, CS2 = VIH, or(2) CS2 = VILISB1*2— 2 100 µA 0 V ≤ Vin(1) 0 V ≤ CS2 ≤ 0.2 V or(2) CS1 ≥ VCC – 0.2 V,CS2 ≥ VCC – 0.2 VISB1*3—2 50µAISB1*4—1 20µAOutput high voltage VOH2.4——VIOH = –1 mAOutput low voltage VOL——0.4VIOL = 2.1 mANotes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.2. This characteristics is guaranteed only for L version.3. This characteristics is guaranteed only for L-SL version.4. This characteristics is guaranteed only for L-UL version.Capacitance (Ta = +25°C, f = 1 MHz)Parameter Symbol Typ Max Unit Test conditions NoteInput capacitance Cin — 8 pF Vin = 0 V 1Input/output capacitance CI/O—10pFVI/O = 0 V 1Note: 1. This parameter is sampled and not 100% tested.HM628128D Series7AC Characteristics (Ta = –20 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)Test Conditions• Input pulse levels: VIL = 0.8 V, VIH = 2.4 V• Input rise and fall time: 5 ns• Input timing reference levels: 1.5 V• Output timing reference level: 1.5 V• Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7)1 TTL Gate+ CL (50 pF) (HM628128D-5)(Including scope and jig)Read CycleHM628128D-5 -7Parameter Symbol Min Max Min Max Unit NotesRead cycle time tRC55 — 70 — nsAddress access time tAA— 55 — 70 nsChip select access time tACS1— 55
View Full Document
Unlocking...