8TMCA3306, CA3306A,CA3306C6-Bit, 15 MSPS,Flash A/D ConvertersAugust 1997FN3102.1Features• CMOS Low Power with Video Speed (Typ) . . . . .70mW• Parallel Conversion Technique• Signal Power Supply Voltage . . . . . . . . . . . 3V to 7.5V• 15MHz Sampling Rate with Single 5V Supply• 6-Bit Latched Three-State Output with Overflow Bit• Pin-for-Pin Retrofit for the CA3300Applications• TV Video Digitizing• Ultrasound Signature Analysis• Transient Signal Analysis• High Energy Physics Research• High Speed Oscilloscope Storage/Display• General Purpose Hybrid ADCs• Optical Character Recognition• Radar Pulse Analysis• Motion Signature Analysis• Robot VisionDescriptionThe CA3306 family are CMOS parallel (FLASH) analog-to-digitalconverters designed for applications demanding both low powerconsumption and high speed digitization. Digitizing at 15MHz, forexample, requires only about 50mW.The CA3306 family operates over a wide, full scale signal input volt-age range of 1V up to the supply voltage. Power consumption is aslow as 15mW, depending upon the clock frequency selected. TheCA3306 types may be directly retrofitted into CA3300 sockets, offer-ing improved linearity at a lower reference voltage and high operat-ing speed with a 5V supply.The intrinsic high conversion rate makes the CA3306 types ideallysuited for digitizing high speed signals. The overflow bit makes pos-sible the connection of two or more CA3306s in series to increasethe resolution of the conversion system. A series connection of twoCA3306s may be used to produce a 7-bit high speed converter.Operation of two CA3306s in parallel doubles the conversion speed(i.e., increases the sampling rate from 15MHz to 30MHz).Sixty-four paralleled auto balanced comparators measure the inputvoltage with respect to a known reference to produce the parallel bitoutputs in the CA3306. Sixty-three comparators are required toquantize all input voltage levels in this 6-bit converter, and the addi-tional comparator is required for the overflow bit.Ordering InformationPinoutsPART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE (oC) PACKAGE PKG. NO.CA3306E ±0.5 LSB 15MHz (67ns) -40 to 85 18 Ld PDIP E18.3CA3306CE ±0.5 LSB 10MHz (100ns) -40 to 85 18 Ld PDIP E18.3CA3306M ±0.5 LSB 15MHz (67ns) -40 to 85 20 Ld SOIC M20.3CA3306CM ±0.5 LSB 10MHz (100ns) -40 to 85 20 Ld SOIC M20.3CA3306D ±0.5 LSB 15MHz (67ns) -55 to 125 18 Ld SBDIP D18.3CA3306CD ±0.5 LSB 10MHz (100ns) -55 to 125 18 Ld SBDIP D18.3CA3306J3 ±0.5 LSB 15MHz (67ns) -55 to 125 20 Ld CLCC J20.BCA3306J3 ±0.5 LSB 10MHz (100ns) -55 to 125 20 Ld CLCC J20.BCA3306 (PDIP, SBDIP)TOP VIEWCA3306 (SOIC)TOP VIEWCA3306 (CLCC)TOP VIEW101112131415161718987654321(MSB) B6OVERFLOWVSSVZCE2CLKCE2PHASEVREF+B5REFB3B2B4B1 (LSB)VDDVINVREF-CENTER1112131415161718201910987654321(MSB) B6OVERFLOWVSSNCVZCE2CLKCE1PHASEVREF+B5REFB3B2B4B1 (LSB)VDDNCVINVREF-CENTER4567891011121332120191514181716VSSVZNCCE2CE1REFB3B1 (LSB)VDDB2B5B4NCCLKVREF+VREF-PHASEVINB6OVER-CENTERFLOW(MSB)CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143| Intersil (and design) is a trademark of Intersil Americas Inc.Copyright © Intersil Americas Inc. 2002. All Rights Reserved9Functional Block DiagramTypical Application CircuitENCODERLOGICCOMP1VSSφ1 (AUTO BALANCE)φ2 (SAMPLE UNKNOWN)≅50kΩCLOCKVREF-VREF+VINVDDφ1φ1 φ1φ2φ2RR/2RRRTHREE-STATER/2DQCLDQCLDQCLDQCLDQCLDQCLDQCLANDLATCHESCOMPARATORCOMP2COMP32COMP63COMP64REFCENTER≅120ΩRRPHASEZENERDIODEVSS6.2V NOMINALOVERFLOWCE1CE2B6 (MSB)B5B4B3B2B1 (LSB)B6OFVSSVZCE2CLKCE1PHVREF+B5RCB3B2B4B1VDDVINVREF-CLOCKCA741CE+12V560Ω5kΩ+5V6.2V+12V0.1µF+-0.2µF10µF+5VSIGNALINPUTDATAOUTPUTOFB6B5B4B3B2B1(LSB)0.1µF101112131415161718987654321CA3306CA3306, CA3306A, CA3306C10Absolute Maximum Ratings Thermal InformationDC Supply Voltage Range, VDDVoltage Referenced to VSS Terminal . . . . . . . . . . . -0.5V to +8.5VInput Voltage RangeAll Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5VDC Input CurrentCLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . ±20mAOperating ConditionsSupply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8VTemperature Range (TA)Ceramic Package (D Suffix) . . . . . . . . . . . . . . . . . -55oC to 125oCPlastic Package (E or M Suffix) . . . . . . . . . . . . . . . -40oC to 85oCThermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)SBDIP Package. . . . . . . . . . . . . . . . . . . . 75 24PDIP Package . . . . . . . . . . . . . . . . . . . . . 95 N/ASOIC Package. . . . . . . . . . . . . . . . . . . . . 115 N/ACLCC Package . . . . . . . . . . . . . . . . . . . . 80 28Maximum Junction TemperatureHermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oCPlastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oCMaximum Storage Temperature Range . . . . . . . . . .-65oC to 150oCMaximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC(SOIC - Lead Tips Only)CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE:1. θJA is measured with the component mounted on an evaluation PC board in free air.Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.8V, VSS = VREF- = GND, Clock = 15MHz Square Wave for CA3306 or CA3306A, 10MHz for CA3306CPARAMETER TEST CONDITIONS MIN TYP MAX UNITSSYSTEM PERFORMANCEResolution 6--BitsIntegral Linearity Error, INL CA3306, CA3306C - ±0.25 ±0.5 LSBCA3306A - ±0.2 ±0.25 LSBDifferential Linearity Error, DNLCA3306, CA3306C - ±0.25 ±0.5 LSBCA3306A - ±0.2 ±0.25 LSBOffset Error (Unadjusted) CA3306, CA3306C (Note 1) - ±0.5 ±1LSBCA3306A - ±0.25 ±0.5 LSBGain Error (Unadjusted) CA3306, CA3306C (Note 2) - ±0.5 ±1LSBCA3306A - ±0.25 ±0.5 LSBGain Temperature Coefficient - +0.1 - mV/oCOffset Temperature Coefficient - -0.1 - mV/oCDYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale)Maximum Conversion Speed CA3306C 10 13 - MSPSCA3306, CA3306A 15 20 - MSPSMaximum Conversion Speed CA3306C (Note 4)φ1, φ2 ≥ Minimum12 - - MSPSCA3306, CA3306A 18 - - MSPSAllowable Input Bandwidth (Note 4) DC - fCLOCK/2MHz-3dB Input Bandwidth -30-MHzSignal to Noise Ratio, SNR