ECEN 248 Lab Report Lab Number 7 Lab Title Introduction to Sequential Logic Section Number 517 Student s Name Jordan Turbeville Student s UIN 431008971 Date 10 28 2022 TA Kevin Kim Objectives Design 1 Learn how to program and test sequential logic circuits in Verilog I Start the program on PC using MobaXterm A Login and enter all necessary prompts B Start by entering vivado and enter II Programing each latch flip flop A Start all circuit files with timescale 1ns ps default nettype none B Use comments in all files to explain logic for single line comments starting with and ending with for multi line comments C Open module e g module D latch D Declare ports E Declare internal nets F III Circuit Simulation Input all circuit logic with delay inputs e g nand 2 nand0 Q nandSEN notQ A Copy tb files from Needed Files ECEN248 to simulation tab B Left click on tb file and move to top C On the Flow tab go to simulation then behavioral simulation D After running use the fit to screen button on the sidebar E Save data F For some Go to Scopes uut Objects and drag the specified items to the waveform G Save data again IV 2 bit Adder Circuit A Copy full adder from lab 5 B Add delays C Copy the test bench code into the project and complete by making a truth table of the possible outputs of each full adder combination D Simulate and test errors E Use the waveform generated to compute the worst case propagation delay V Synchonous Adder A Complete all for step II except instead of regular circuit logic use behavioral statements e g always posedge Clk or A reg A B Simulate C Change CLOCK PERIOD to 18 and repeat simulation while adding 1 to CLOCK PERIOD each time until all tests are passed in the console Results Conclusion While encountering several errors such as syntax and failed logic I correctly simulated all my circuits The most difficult I had was the 4 bit ALU unit I was able to successfully debug my Verilog using the command prompt to identify the locations of the errors in my module For this lab I learned how to do simple code logic in Verilog I learned how to code in several bits I used in previous labs and remotely simulate them to test functionality I learned how to input basic circuit logic and commands into my console and execute modules within another module e g 4 bit add sub used in a 4 bit ALU Post lab Deliverables All waveforms and source code attached in submission 1 The results of the SR Latch matched the truth table and the waveform had the programed delays between each gate or logic combination resulting in a staggered waveform 2 The latches are not working correctly a Q and notQ are not changing states at the same time b Q and not Q both are no changing values at either positive edge or active high time or active low times c There is a delay from my point of clock to any of the outputs 3 Compared to the structural waveform the behavioral version of the D Flip Flip was much more linear 5 Answers 4 The worst case propagation delay through the adder I got was 10ns which I got when the A and B output changed to 2 and 2 and the carry took 10ns to adjust a The time scale that the circuit can be reduced to and still work in 20ns b An increase in the width of the adder would result in greater time delay because it has a greater number of inputs This would result in a drop in clock rate c The best way to improve the clock rate of the design would be to decrease the number of gates in the design