LAB 10 Counters Clock Dividers and Debounce Circuits Joshua Martin ECEN 248 509 TA Yiting Luo Date November 13 2020 Objectives In this lab I will learn how to design implement test and synthesize a digital combination lock that can be used on a safe or access controlled doorway The combination lock full state machine will be described in Verilog A state diagram will be utilized to describe the combination lock FSM and the switches on the ZYBO board will be used to enter input to the lock A top level Verilog module will also be created which will drive the counter on the FPGA and then loaded onto the ZYBO board An XDC file will be used to connect the functions on the top level Verilog module to the ZYBO board I will learn the concepts and implementation of full state machines This lab will introduce modern circuit design techniques using Verilog Design The objective is to design and implement the digital circuits for a 4 bit 3 number combination lock FSM and a 4 bit 4 number combination lock FSM that can be used on a safe or access controlled doorway both described in Verilog The combination lock FSM will be described using a state diagram system and then hooked up in combination with a top level Verilog module connected to a series of synchronizers The synchronizers will be connected to two input keys and the reset button The top level Verilog module will drive the counter on the FPGA and then will be loaded onto the ZYBO board The switches on the ZYBO board will be used to enter input to the lock An XDC file will be used to connect the functions on the top level Verilog module to the ZYBO board Both designs will be synthesized and implemented onto the ZYBO board and tested for functionality on the board All 4 LEDs will light up if the password is inputted correctly Results All the Verilog modules functioned as expected The final top level up counter module worked and functioned without issue after much debugging They were tested against test benches and simulated the circuit without fault All the modules were simulated using behavioral and structural Verilog The synthesis and implementation of both 3 and 4 number combination locks on the ZYBO board had functional keys and reset buttons and would only light up when the proper sequence of numbers and keys were inputted Combination Lock FSM Conclusion In this lab I created simple behavioral Verilog modules for a 4 bit 3 number combination lock FSM and a 4 bit 4 number combination lock FSM that can be used on a safe or access controlled doorway both described in Verilog The combination lock FSM was described using a state diagram system and then hooked up in combination with a top level Verilog module connected to a series of synchronizers The base modules functioned correctly All Verilog modules were tested with a test bench simulation to error check and debug The synthesis and implementation of the combination lock on the ZYBO board had functional keys and reset buttons and used the switches on the board to input the password in binary The lock would only light up if all numbers were inputted correctly with the correct key inputs In this lab I learned modern behavioral circuit design techniques using Verilog the concepts and implementation of Full State machines and descriptions in verilog using a state diagram Questions 1 Include the source code with comments for all modules you simulated and or implemented in lab You do not have to include test bench code that was provided Code without comments will not be accepted If the last 4 digits of your UIN cannot be found in your verilog code you will receive any point for that design 3 password combination lock code and 4 password combination lock code 1 3 Number Combination Lock FSM This module describes the a preprogrammed module of a simulated combination lock fsm in Verilog module combination lock fsm define module name and interface output reg 1 0 State 1268 2 bit state input output wire 3 0 Lock 1268 4 bit state of lock input wire Key1 1268 Key2 1268 Reset 1268 Clk 1268 1 bit signals to the lock input wire 3 0 Password 1268 password combination input internal nets assignment parameter S0 2 b00 S1 2 b01 S2 2 b10 S3 2 b11 assigns different state values to binary reg 2 0 next state 1268 3 bit regs to be changed in blocks always block triggered at the present state change key change or password always case State 1268 conditional statement based on present state S0 begin if Key1 1268 Password 1268 4 b1101 next state 1268 S1 if password and button pressed goes to next state next state 1268 S0 resets lock else end S1 begin else else happens end S2 begin if Key2 1268 Password 1268 4 b0111 next state 1268 S2 if password and button pressed goes to next state if Key2 1268 Password 1268 4 b0111 next state 1268 S0 resets lock if wrong password next state 1268 S1 if wrong password but no button pressed nothing if Key1 1268 Password 1268 4 b1001 else else happens end S3 begin else end next state 1268 S3 if password and button pressed goes to next state if Key1 1268 Password 1268 4 b1001 next state 1268 S0 resets lock if wrong password next state 1268 S2 if wrong password but no button pressed nothing if Reset 1268 1 b1 next state 1268 S0 resets lock if reset button pressed next state 1268 S3 does nothing default next state 1268 S0 endcase always block triggered at the Clk edge or reset triggers a reset or next state always posedge Clk 1268 if Reset 1268 resets states to S0 State 1268 S0 else State 1268 next state 1268 goes to next state assign Lock 1268 State 1268 S3 4 b1111 4 b0000 assign Lock 1111 if state S3 else 0000 endmodule 2 4 Number Combination Lock FSM This module describes the a preprogrammed module of a simulated 4 combination lock fsm in Verilog module combination lock fsm define module name and interface output reg 2 0 State 1268 2 bit state input output wire 3 0 Lock 1268 4 bit state of lock input wire Key1 1268 Key2 1268 Reset 1268 Clk 1268 1 bit signals to the lock input wire 3 0 Password 1268 password combination input internal nets assignment parameter S0 3 b000 S1 3 b001 S2 3 b010 S3 3 b011 assigns different state values to binary S4 3 b100 reg 2 0 next state 1268 3 bit regs to be changed in blocks always block triggered at the present state change key change or password always present state 1268 or Key1 1268 or Key2 1268 or Password 1268 always case State 1268 conditional statement based on present state S0 begin if Key1 1268 Password 1268 4 b1101 next state 1268 S1 if