ECEN 248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507)Chapter 6.1 Multiplexers2-to-1 multiplexer4-to-1 multiplexer4-to-1 multiplexer implemented by 2-to-1 multiplexer16-to-1 multiplexerA practical application of multiplexersImplementing programmable switches in an FPGAChapter 6.1.1 Synthesis of Logic Functions Using MultiplexersSynthesis of a logic function using multiplexersThree-input majority function by using a 4-to-1 multiplexerThree-input XOR by 2-to-1 multiplexersThree-input XOR implemented with a 4-to-1 multiplexerChapter 6.1.2 Multiplexer Synthesis Using Shannon’s ExpansionsMultiplexers synthesis using Shannon’s ExpansionSynthesis for Synthesis for 3-input majority functionCircuits Ex. 6.8 by using 3-input lookup tableCircuits Ex. 6.8 by using 3-input lookup tableChapter 6.2 DecodersDecoders2-to-4 decoder3-to-8 decoder by using 2-to-4 decodersUsing decoder to build multiplexerDemultiplexerExample: 1-to-4 demultiplexer by using 2-to-4 decoderECEN 248 –Introduction to Digital Systems Design (Spring 2008)(Sections: 501, 502, 503, 507)Prof. Xi ZhangECE Dept, TAMU, 333N WERChttp://www.ece.tamu.edu/~xizhang/ECEN248Chapter 6.1 MultiplexersFigure 6.1. A 2-to-1 multiplexer.(a) Graphical symbolfsw0w101(b) Truth table01fsw0w1(d) Circuit with transmission gatesw 0 w 1 f s fsw0w1(c) Sum-of-products circuit2-to-1 multiplexerFigure 6.2. A 4-to-1 multiplexer.(b) Truth table w 0 w 1 0 0 1 1 1 0 1 f s 1 0 s 0 w 2 w 3 f s 1 w 0 w 1 0001s 0 w 2 w 3 1011(a) Graphic symbol f (c) Circuit s 1 w 0 w 1 s 0 w 2 w 3 4-to-1 multiplexerFigure 6.3. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.0 w 0 w 1 0 1 w 2 w 3 0 1 f 0 1 s 1 s 4-to-1 multiplexer implemented by 2-to-1 multiplexerFigure 6.4. A 16-to-1 multiplexer.w 8 w 11s 1 w 0 s 0 w 3 w 4 w 7 w 12w 15s 3 s 2 f 16-to-1 multiplexer Building 16-to-1 multiplexer by using four 4-to-1 multiplexers.Figure 6.5. A practical application of multiplexers.x 1 0 1 x 2 0 1 s y 1 y 2 (b) Implementation using multiplexers x 1 x 2 y 1 y 2 (a) A 2x2 crossbar switch s A practical application of multiplexers s = 0 x1 Æ y1 x2 Æ y2 s = 1 x2 Æ y1 x1 Æ y2Figure 6.6. Implementing programmable switches in an FPGA.i 1 i 2 f (a) Part of the FPGA in Figure 3.39 i 1 i 2 f (c) Implementation using multiplexers 0/1 0/1 0/1 0/1 Implementing programmable switches in an FPGAStorage cellStorage cellChapter 6.1.1 Synthesis of Logic Functions Using MultiplexersFigure 6.7. Synthesis of a logic function using multiplexers.(b) Modified truth table 0 1 0 0 1 1 1 0 1 f w 1 0 w 2 1 0 0 1 f w 1 w 2 w 2 (a) Implementation using a 4-to-1 multiplexer f w 1 0 1 0 1 w 2 1 0 0 0 1 1 1 0 1 f w 1 0 w 2 1 0 f w 2 w 1 (c) Circuit Synthesis of a logic function using multiplexers21wwf ⊕=Not efficient More efficientFigure 6.8. Implementation of the three-input majority function using a 4-to-1 multiplexer.w3w3(a) Modified truth table00011101fw10w21000110110001000110110111w1w2w3f00001111fw10w21(b) Circuitw3Three-input majority function by using a 4-to-1 multiplexer n-input Majority function:  The output is 1 if more than half inputs are 1; Otherwise, the output is equal to 0.Figure 6.9. Three-input XOR implemented with 2-to-1 multiplexers.(a) Truth table000110110110000110111001w1w2w3f00001111w2w3⊕w2w3⊕fw3w1(b) Circuitw2Three-input XOR by 2-to-1 multiplexers321wwwf⊕⊕=Figure 6.10. Three-input XOR function implemented with a 4-to-1 multiplexer.f w 1 w 2 (b) Circuit w 3 (a) Truth table 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 1 0 0 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 w 3 w 3 w 3 w 3 Three-input XOR implemented with a 4-to-1 multiplexer321wwwf⊕⊕=Chapter 6.1.2 Multiplexer Synthesis Using Shannon’s ExpansionsMultiplexers synthesis using Shannon’s Expansion0 0 0 1 1 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 w 1 w 2 w 3 f 0 0 0 0 1 1 1 1 0 1 f w 1 w 2 w 3 w 2 w 3 + (b) Truth table (b) Circuit f w 3 w 1 w 2 Figure 6.11. The three-input majority function implemented using a 2-to-1 multiplexer.()()321321wwwwwwf++=321321321321wwwwwwwwwwwwf+++=Figure 6.12. The circuits synthesized in Example 6.6.(a) Using a 2-to-1 multiplexerf w 2 w 1 w 3 f w 1 w 2 w 3 (b) Using a 4-to-1 multiplexer1 Synthesis for () ( )32131312131wwwwwwwwwwwf++=++=() () () ()1213213213212121212131213121212121wwwwwwwwwwwfwwfwwfwwfwwwwwwwwfwwwwwwww+++=+++=++=312131wwwwwwf ++=Figure 6.13. The circuit synthesized in Example 6.7w 2 0 w 3 1 f w 1 Synthesis for 3-input majority function()( )()( )32132132321321323121wwwwwwwwwwwwwwwwwwwwf++=+++=++=2121wwhandwwgLet+==() ( )() ()10232322wwwhwwwg+=+=Figure 6.14. Circuits synthesized in Example 6.8w 2 w 3 f w 4 w 1 f w 1 (a) Using three 3-LUTsf w 1 0 Circuits Ex. 6.8 by using 3-input lookup table42143232132wwwwwwwwwwwf+++=()()42432321323211111wwwwwwwwwwwwwfwfwfww++++=+=Figure 6.14. Circuits synthesized in Example 6.8(b) Using two 3-LUTsw 1 w 3 f w 4 0 f w 2 w 2 Circuits Ex. 6.8 by using 3-input lookup table42143232132wwwwwwwwwwwf+++=()()4331241322222wwwwwwwwwfwfwfww+++=+= theoremsDeMorgan'on based gOberservin22wwff =We need only two 3-lookup tables,Chapter 6.2 DecodersFigure 6.15. An n-to-2nbinary decoder.0 w n 1 –n inputsEnEnable2 n outputs y 0 y 2 n 1 –w DecodersFigure 6.16. A 2-to-4 decoder.0 0 1 1 1 0 1 y 0 w 1 0 w 0 x x 1 1 0 1 1 En0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 (a) Truth table w 0 Eny 0 w 1 y 1 y 2 y 3 (b) Graphical symbol (c) Logic circuit w 1 w 0 y 0 y 1 y 2 y 3 En2-to-4 decoderFigure 6.17. A 3-to-8 decoder using two 2-to-4 decoders.w 2 w 0 w y 0 y 1 y 2 y 3 0 Eny 0 w 1 y 1 y 2 y 3 w 0 Eny 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 En3-to-8 decoder by using 2-to-4 decodersFigure 6.18. A 4-to-16 decoder built using a decoder tree.w 0 Eny 0 w 1 y 1 y 2 y 3 y 8 y 9 y 10y 11w 2 w 0 y 0 y 1 y 2 y 3 w 0 Eny 0 w 1 y 1 y 2 y 3 w 0 Eny 0 w 1 y 1 y 2 y 3 y 4 y 5 y 6 y 7 w 1 w 0 Eny 0 w 1 y 1 y 2 y 3 y 12y 13y 14y 15w 0 Eny 0 w 1 y 1 y 2 y 3 w 3 EnFigure 6.19. A 4-to-1 multiplexer built using a decoder.w 1 w 0 w 0 Eny 0 w 1 y 1 y 2 y 3 w 2 w 3 f s 0 s 1 1 Using decoder to build multiplexerDemultiplexer Multiplexer The purpose of Multiplexer is to multiplex the n data inputs onto the single data output under control of the select inputs. Demultiplexer Perform the opposite function of the multiplexer. Place the value of a single data input onto multiple data outputs.  Can be implemented by using a decoder circuit.Example: 1-to-4