LAB 11 Traffic Light Controller Joshua Martin ECEN 248 509 TA Yiting Luo Date November 20 2020 Objectives In this lab I will learn how to design implement test and synthesize a traffic light controller between a farm and highway road The traffic light controller full state machine will be described in Verilog We will be using the LED lights and the push buttons in order to determine the outputs of the behavioral verilog An XDC file will be used to connect the functions on the top level Verilog module to the ZYBO board I will learn the concepts and implementation of full state machines This lab will introduce modern circuit design techniques using Verilog Design The objective is to design and implement the digital circuits for a traffic light controller In the first experiment it requires the implementation of the FSM by using behavioral verilog to construct We used the tcl FSM code from the pre lab in order to develop the project After designing the project we connected to the zybo to test out the result whether the verilog is correct In the second experiment we added a sensor into the existing verilog we had in the first part of the experiment The top level Verilog module will drive the counter on the FPGA and then will be loaded onto the ZYBO board The switches on the ZYBO board will be used to enter input to the lock An XDC file will be used to connect the functions on the top level Verilog module to the ZYBO board Both designs will be synthesized and implemented onto the ZYBO board and tested for functionality on the board Results All the Verilog modules functioned as expected The final top level up counter module worked and functioned without issue after much debugging They were tested against test benches and simulated the circuit without fault All the modules were simulated using behavioral and structural Verilog The synthesis and implementation of both light controllers on the ZYBO board had functional keys and reset buttons and would only light up when the proper sequence of controller input Light Controller without sensor Light Controller with sensor Conclusion In this lab I created simple behavioral Verilog modules for a traffic light controller with and without a sensor FSM that can be used on a highway and farm road intersection both described in Verilog The traffic light FSM was described using a state diagram system and then hooked up in combination with a top level Verilog module connected to a series of synchronizers The base modules functioned correctly All Verilog modules were tested with a test bench simulation to error check and debug The synthesis and implementation of the combination lock on the ZYBO board had functional keys and reset buttons The traffic light controller would only light up if all numbers were inputted correctly with the correct key inputs In this lab I learned modern behavioral circuit design techniques using Verilog the concepts and implementation of Full State machines and descriptions in verilog using a state diagram Questions 1 Include the source code with comments for all modules that you wrote or modified in lab You do not need to include code that was provided Remember that code without comments will not be accepted TLC FSM code in Experiment 1 TLC FSM code in Experiment 2 TLC FSM test bench code in Experiment 12 1 Experiment 1 timescale 1ns 1ps default nettype none This module describes the a preprogrammed module of a simulated traffic controller light fsm in Verilog module tlc controller define module name and interface output wire 3 0 JB 4 bit state output for debugging output wire 1 0 highwaySignal 1268 farmSignal 1268 2 bit light signals connected to LED input wire Rst 1268 Clk 1268 1 bit signals to the controller intermediate nets reg 30 0 Count 1268 31 bit regs to be changed in blocks wire RstSync 1268 wire RstCount 1268 assign JB 3 RstCount 1268 synchronizes button inputs synchronizer syncRst RstSync 1268 Rst 1268 Clk 1268 instantiate tlc Fsm tlc fsm FSM State 1268 JB 2 0 RstCount 1268 RstCount 1268 highwaySignal 1268 highwaySignal 1268 farmSignal 1268 farmSignal 1268 Rst 1268 RstSync 1268 Clk 1268 Clk 1268 Count 1268 Count 1268 always posedge Clk 1268 if RstCount 1268 resets count to 0 Count 1268 0 else Count 1268 Count 1268 1 goes to next count endmodule timescale 1ns 1ps default nettype none This module describes the a preprogrammed module of a simulated traffic controller light fsm in Verilog define one sec 50000000 define three sec 150000000 define fifteen sec 750000000 define thirty sec 1500000000 module tlc fsm define module name and interface output reg 2 0 State 1268 3 bit state output for debugging output reg RstCount 1268 use an always block output reg 1 0 highwaySignal 1268 farmSignal 1268 2 bit state of light signals input wire Rst 1268 Clk 1268 1 bit signals to the controller input wire 30 0 Count 1268 use n internal nets assignment parameter Srst 3 b110 S0 3 b000 state 0 is reset S1 3 b001 S2 3 b010 S3 3 b011 assigns different state values to binary S4 3 b100 S5 3 b101 parameter green 2 b11 yellow 2 b10 red 2 b01 intermediate nets reg 2 0 next state 1268 3 bit regs to be changed in blocks always block triggered at the present state change or count nest state and output logic always State 1268 or Count 1268 case State 1268 conditional statement based on present state Srst next state 1268 S0 starts state function S0 begin else end S1 begin else end S2 begin else end S3 begin else if Count 1268 one sec next state 1268 S1 signal goes to next state next state 1268 S0 Nothing happens to signal if Count 1268 thirty sec next state 1268 S2 signal goes to next state next state 1268 S1 Nothing happens to signal if Count 1268 three sec next state 1268 S3 signal goes to next state next state 1268 S2 Nothing happens to signal if Count 1268 one sec next state 1268 S4 signal goes to next state next state 1268 S3 Nothing happens to signal end S4 begin else end S5 begin else if Count 1268 fifteen sec next state 1268 S5 signal goes to next state next state 1268 S4 Nothing happens to signal if Count 1268 three sec next state 1268 S0 signal goes to next state next state 1268 S5 Nothing happens to signal end default next state 1268 Srst endcase output logic description always State 1268 or Count 1268 case State 1268 Srst begin highwaySignal 1268 red farmSignal 1268 red RstCount 1268 1 end S0 begin else end S1 begin else end S2 begin highwaySignal 1268 red both signals red farmSignal 1268 red if Count 1268 one sec if count