ECEN 248 Lab Report Lab Number 9 Lab Title An Introduction to High Speed Addition Section Number 517 Student s Name Jordan Turbeville Student s UIN 431008971 Date 11 13 2022 TA Kevin Kim Objectives In this lab we will be focusing on high speed addition We will learn how to implement high speed addition using carry lookahead and Verilog The purpose of this lab is to be able to do addition with less delay than a ripple carry adder Design To begin I used my 4 bit lookahead adder test bench file to simulate my 4 bit lookahead After I added my 2ns delay in order to determine the propagation delay of the unit After I wrote my block carry lookahead unit expanding my propagate and summation unit from 4 to 16 bits After writing my 16 bit carry lookahead adder simulating it with the test bench and ensuring all tests passed I added gate delays to 2ns and changed test delay to the propagation delay of my previous unit repeating the simulation while slowly decreasing the test delay until the tests failed The result of this lab is my correct source code no waveforms My code is included as text files in the submission all labeled with the title of the module For this lab I implemented a carry lookahead unit to do high speed addition as well as learned to modify my propagation unit to utilize more bits Results Conclusion Post lab Deliverables 1 The change in gate delay was 2ns and the worst case delay was 8 gates so the propagation delay is 16ns This reflects the 16ns gate delay used in part 2 2 Carry lookahead adder had 82 gates and the ripple carry adder has 80 gates Carry lookahead adder is still faster with more gates 3 4 bit ripple carry adder has 9 gate delays 4 bit carry lookahead has 4 gate delays 16 bit ripple carry adder has 33 gate delays 16 bit carry lookahead has 8 gate delays I liked seeing the waveforms when all tests passed I did not like calculating gate delays 4 5 The lab manual was very clear 6 I don t have any suggestions for this lab