Lab Title Counters Clock Dividers and Debounce Circuits ECEN 248 Lab Report Lab Number 8 Section Number 517 Student s Name Jordan Turbeville Student s UIN 431008971 Date 11 06 2022 TA Kevin Kim Objectives Design 1 Learn how to program and test sequential logic circuits in Verilog I Start the program on PC using MobaXterm A Login and enter all necessary prompts B Start by typing vivado and enter II Circuit Implementation and loading FPGA board Part 1 A Start all circuit files with timescale 1ns ps default nettype none B Use comments in all files to explain logic for single line comments starting with and ending with for multi line comments C Open the module and program all manual logic D Copy xdc file E Synthesize and Implement circuit logic F Connect logic analyzer probe to logic analyzer along with all necessary logic and GND jumper wires into the board G Complete all steps to set up the logic analyzer H Turn on FPGA board and observe the logic analyzer I Adjust the waveform for the logic analyzer should be four clocks with each one twice the speed of the previous J Complete simple time measurements III Developing Up Counter Part 2 A For the new v file repeat steps II A C B For the up counter simulate and observe the waveform C Set the display format of the count bus to hexadecimal D Answer questions in manual E For top level v repeat steps II A E F Experiment with the combinations of SW1 and SW0 G Press BTN1 and note results IV Effects of Button Bounce on a Synchronous Circuit Part 3 A Add bounce tb v file as a simulation source B Add noDebounce v as a design source C Modify the uut name in bounce tb v so that noDebounce v is being used D Observe results E Add withdebounce v as a design source simulate and observe F Add comments to withDebounce v G Compare waveforms of noDebounce v and withDebounce v Results Conclusion For part 1 the logic analyzer had the correct display for the counter the original and 3 sub divisions For part 2 correctly coded and simulated the up counter as well as coded synthesized and implemented the top level module v and xdc files For part 3 correctly simulated the button with noDebounce v and withDebounce v For this lab the primary objective was to reinforce our knowledge of sequential circuits by using a binary counter leading me to implement the given binary up counter using combinational components and sequential components discussed in the previous lab Additionally demonstrating two use cases for binary counters namely clock frequency division and I O denouncing Post lab Deliverables All waveforms and source code attached in the submission Questions included in the manual are attached as a pdf or png