ECEN 248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507)Chapter 7 (Conted.) A simple shift registerParallel-access shift registerBreak page between Ch 7 and 8Chapter 8. Synchronous Sequential circuitsSynchronous sequential circuitsSynchronous sequential circuitsFinite State Machine (FSM)General form of a Moore-type FSMGeneral form of a Mealy-type FSMSteps to design a FSM (Moore & Mealy)Example of designing “sequence detector” (Moore Type)Input and output signals of the sequence detectorState diagram of sequence detectorState table for the sequence detectorA general sequential circuit implementationState-assigned table for the sequence detectorDerivation of logic expressions (use D flip-flops) for sequence detectorFinal implementation (use “don’t cares”) of the sequence detectorTiming diagram for the circuitSummary of design stepsImproved state assignmentComparison between different assignmentsFinal circuit for the improved state assignmentECEN 248 –Introduction to Digital Systems Design (Spring 2008)(Sections: 501, 502, 503, 507)Prof. Xi ZhangECE Dept, TAMU, 333N WERChttp://ece.tamu.edu/~xizhang/ECEN248Chapter 7 (Conted.) A simple shift registerFigure 7.18. A simple shift register.t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Q 1 Q 2 Q 3 Q 4 Out = In(b) A sample sequence D Q Q Clock D Q Q D Q Q D Q Q InOut (a) Circuit Q 1 Q 2 Q 3 Q 4 Shift register is composed by a number of D flip-flops.Parallel-access shift registerFigure 7.19. Parallel-access shift register.Q3Q2Q1Q0ClockParallel inputParallel outputShift/LoadSerialinputDQQDQQDQQDQQBreak page between Ch 7 and 8Chapter 8. Synchronous Sequential circuits The definition of sequential circuitsA general class of circuits in which the outputs depend on the past behavior/state of the circuit, as well as on the present valuesof the inputs.  There are two different types of sequential circuits: 1) Synchronous sequential circuitsControlled by a clock signal. 2) Asynchronous sequential circuitsNo clock signal is used.Synchronous sequential circuitsFigure 8.1. The general form of a sequential circuit.Combinational circuit Flip-flopsor Storage circuitsClock Q W Z Combinational circuit  A synchronous sequential circuit consists of a number of combinational circuits and flip-flops. Flip-flops are used to store past behaviors.  Flip-flops have to be the edge-trigged type.Synchronous sequential circuitsFigure 8.1. The general form of a sequential circuit.Combinational circuit Flip-flopsor Storage circuitsClock Q W Z Combinational circuit  Input: W Output: Z State: Q (the output of the flip-flops)States represents the past behaviors of the circuit.Finite State Machine (FSM) Sequential circuits are also called finite state machine (FSM), or simply machine. There are two types of synchronous sequential circuits: Moore typeOutputs depend ONLY on current states. Mealy typeOutputs depend on BOTH current states and current inputsGeneral form of a Moore-type FSMCombinational circuit Flip-flopsClock Q W Z Combinational circuitGeneral form of a Mealy-type FSMCombinational circuit Flip-flopsClock Q W Z Combinational circuitSteps to design a FSM (Moore & Mealy) State diagram State table State assignment Choice of flip-flops and derivation of next-state and output expressions Timing diagram Final implementation of the circuit.Example of designing “sequence detector” (Moore Type) The circuit has one input, w, and one output, z. All changes in the circuit occur on the positive edge of a clock signal. The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1. Otherwise, the value of z is equal to 0.  Thus, the circuit detects if two or more consecutive 1s occur on its input w.Input and output signals of the sequence detectorFigure 8.2. Sequences of input and output signals.Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0State diagram of sequence detector A: starting state, also the state after an input w=0 is applied. B: The first occurrence of w=1 (after last time when w=0). C: w=1 in two most recent successive clock cycles.Figure 8.3. State diagram of a simple sequential circuit.C z 1 = ⁄Reset B z 0 = ⁄A z 0 = ⁄w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =State table for the sequence detectorFigure 8.4. State table for the sequential circuit in Figure 8.3.C z 1 = ⁄Reset B z 0 = ⁄A z 0 = ⁄w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = Present Next state Outputstate w = 0 w = 1 z A A B 0 B A C 0 C A C 1 Moore: Output is inside of state circle,not depends on inputsA general sequential circuit implementationFigure 8.5. A general sequential circuit with input w, output z, and two state flip-flops.CombinationalcircuitCombinationalcircuitClocky2zwy1Y1Y2State-assigned table for the sequence detectorFigure 8.6. State-assigned table for the sequential circuit in Figure 8.4.Present Next state state w = 0 w = 1 Outputy 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 00 01 0 B 01 00 100 C 10 00 101 11 dd dd d Present Next state Outputstate w = 0 w = 1 z A A B 0 B A C 0 C A C 1Derivation of logic expressions (use D flip-flops) for sequence detectorFigure 8.7. Derivation of logic expressions for the sequential circuit in Figure 8.6.w00 01 11 100 1 0 1 0 y 2 y 1 Y1wy1 y 2 = w 00 01 11 100 1 0 d 1 d y 2 y 1 Y 2 wy1 y 2 wy1 y 2 + = d d 0 0 0 0 0 0 1 0 1 0 1 0 d y 1 z y 1 y 2 = 0 1 y 2 Y1wy1 y 2 = Y 2 wy1 wy2 + = z y 2 = w y 1 y 2 + ( ) = Ignoring don't cares Using don't cares Present Next state state w = 0 w = 1 Outputy 2 y 1 Y 2Y 1Y2 Y 1 z A 00 00 01 0 B 01 00 10 0 C 10 00 10 1 11 dd dd dFinal implementation (use “don’t cares”) of the sequence detectorFigure 8.8. Final implementation of the sequential circuit derived in Figure 8.7.D Q Q D Q Q Y 2 Y 1 w Clock z y 1 y 2 ResetnTiming diagram for the circuitFigure 8.9. Timing diagram for the circuit in Figure 8.8.t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0 1 0 1 0 Clock w y 1 y 2 1 0 zSummary of design steps Obtain the specification of the desired circuit. Draw the state diagram Selecting a starting state Given the staring state consider all valuations of inputs to the circuit create new states to respond to these inputs record the corresponding outputs and