# TAMU ECEN 248 - Chapter_7_8_Chapter_Part-I_Xi_Zhang (24 pages)

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## Chapter_7_8_Chapter_Part-I_Xi_Zhang

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## Chapter_7_8_Chapter_Part-I_Xi_Zhang

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Pages:
24
School:
Texas A&M University
Course:
Ecen 248 - Intro To Dgtl Sym Dsgn
##### Intro To Dgtl Sym Dsgn Documents
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ECEN 248 Introduction to Digital Systems Design Spring 2008 Sections 501 502 503 507 Prof Xi Zhang ECE Dept TAMU 333N WERC http ece tamu edu xizhang ECEN248 Chapter 7 Conted A simple shift register In D Clock Q Q1 D Q Q Q2 D Q Q Q Q3 D Q Q4 Out Q a Circuit In Q1 Q2 Q3 Q4 Out t0 1 0 0 0 0 t1 0 1 0 0 0 t2 1 0 1 0 0 t3 1 1 0 1 0 t4 1 1 1 0 1 t5 0 1 1 1 0 t6 0 0 1 1 1 t7 0 0 0 1 1 Shift register is composed by a number of D flip flops b A sample sequence Figure 7 18 A simple shift register Parallel access shift register Parallel output Q3 D Q Q Serial Shift Load input Q2 D Q Q1 D Q Parallel input Q Q Q0 D Q Q Clock Figure 7 19 Parallel access shift register Break page between Ch 7 and 8 Chapter 8 Synchronous Sequential circuits The definition of sequential circuits A general class of circuits in which the outputs depend on the past behavior state of the circuit as well as on the present values of the inputs There are two different types of sequential circuits 1 Synchronous sequential circuits Controlled by a clock signal 2 Asynchronous sequential circuits No clock signal is used Synchronous sequential circuits A synchronous sequential circuit consists of a number of combinational circuits and flip flops Flip flops are used to store past behaviors Flip flops have to be the edge trigged type W Combinational circuit Flip flops or Storage circuits Q Combinational circuit Clock Figure 8 1 The general form of a sequential circuit Z Synchronous sequential circuits Input W Output Z State Q the output of the flip flops States represents the past behaviors of the circuit W Combinational circuit Flip flops or Storage circuits Q Combinational circuit Clock Figure 8 1 The general form of a sequential circuit Z Finite State Machine FSM Sequential circuits are also called finite state machine FSM or simply machine There are two types of synchronous sequential circuits Moore type Outputs depend ONLY on current states Mealy type Outputs depend on BOTH current states and current inputs General form of a Moore type FSM W Clock Combinational circuit Flip flops Q Combinational circuit Z General form of a Mealy type FSM W Clock Combinational circuit Flip flops Q Combinational circuit Z Steps to design a FSM Moore Mealy State diagram State table State assignment Choice of flip flops and derivation of nextstate and output expressions Timing diagram Final implementation of the circuit Example of designing sequence detector Moore Type The circuit has one input w and one output z All changes in the circuit occur on the positive edge of a clock signal The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1 Otherwise the value of z is equal to 0 Thus the circuit detects if two or more consecutive 1s occur on its input w Input and output signals of the sequence detector Clockcycle w z t0 0 0 t1 1 0 t2 0 0 t3 1 0 t4 1 0 t5 0 1 t6 1 0 t7 1 0 t8 1 1 t9 0 1 Figure 8 2 Sequences of input and output signals t10 1 0 State diagram of sequence detector Reset w 1 w 0 A z 0 B z 0 w 0 w 1 w 0 C z 1 w 1 A starting state also the state after an input w 0 is applied B The first occurrence of w 1 after last time when w 0 C w 1 in two most recent successive clock cycles Figure 8 3 State diagram of a simple sequential circuit State table for the sequence detector Moore Output is inside of state circle not depends on inputs Reset w 1 w 0 A z 0 B z 0 w 0 w 1 w 0 C z 1 w 1 Figure 8 4 State table for the sequential circuit in Figure 8 3 Next state Output Present z state w 0 w 1 A B C A A A B C C 0 0 1 A general sequential circuit implementation Y1 w y1 Combinational circuit Combinational circuit Y2 y2 Clock Figure 8 5 A general sequential circuit with input w output z and two state flip flops z State assigned table for the sequence detector Present state Next state Present state w 0 w 1 A B C A A A B C C Output z 0 0 1 A B C Next state w 0 w 1 y 2y 1 Y 2Y 1 Y 2Y 1 00 01 10 11 00 00 00 dd 01 10 10 dd Output z 0 0 1 d Figure 8 6 State assigned table for the sequential circuit in Figure 8 4 Derivation of logic expressions use D flip flops for sequence detector y y 2 1 w Present A B C 0 Next state state w 0 w 1 y2y1 Y2Y1 Y2Y1 00 01 10 11 00 00 00 dd 01 10 10 dd 00 01 11 10 0 0 d 0 Ignoring don t cares Y 1 Output 1 0 d 0 00 01 11 10 0 0 d 0 Using don t cares 1 wy 1y 2 Y 2 wy y 2 wy 1y 1 2 Y 1 wy 1y 2 z 0 0 1 d y y 2 1 w 0 Y 1 y y 0 1 0 1 0 0 d 1 2 wy wy 1 2 w y y 1 2 1 2 0 1 z y 1y 2 1 z y 2 d Figure 8 7 Derivation of logic expressions for the sequential circuit in Figure 8 6 Final implementation use don t cares of the sequence detector Y2 y2 D Q z Q y1 Y1 w D Q Q Clock Resetn Figure 8 8 Final implementation of the sequential circuit derived in Figure 8 7 Timing diagram for the circuit t0 Clock w y1 y2 z t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 0 1 0 1 0 1 0 1 0 Figure 8 9 Timing diagram for the circuit in Figure 8 8 Summary of design steps Obtain the specification of the desired circuit Draw the state diagram Selecting a starting state Given the staring state consider all valuations of inputs to the circuit create new states to respond to these inputs record the corresponding outputs and state transitions Create a state table State minimization in section 8 6 State assignment Decide the number of state variables needed to represent all states perform the state assignment not unique the next state the output Choose the type of flip flops for the circuit D type flop flops so far Derive logic expressions for Improved state assignment Next state Present state w 0 w 1 A B C A A A B C C Output z 0 0 1 A B …

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