ECEN 248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507)ECEN 248 –Introduction to Digital Systems Design (Spring 2008)(Sections: 501, 502, 503, 507)Prof. Xi ZhangECE Dept, TAMU, 333N WERChttp://ece.tamu.edu/~xizhang/ECEN248Figure 8.60. State diagram for the counter.w0=w1=w0=w1=w0=w1=w0=w1=w0=w1=w0=w1=w0=w1=w0=w1=A/0 B/1 C/2 D/3E/4F/5G/6H/7Section 8.7 Design of A Counter Using Sequential CircuitsFigure 8.61. State table for the counter.Present Next state Outputstate w = 0 w = 1 A A B 0 B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7 State Diagram and State Table for A Modulo-8 CounterFigure 8.62. State-assigned table for the counter.Present Next state state w = 0 w = 1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0 A 000 000 001 000 B 001 001 010 001 C 010 010 011 010 D 011 011 100 011 E 100 100 101 100 F 101 101 110 101 G 110 110 111 110 H 111 111 000 111 State-assigned table for the counterFigure 8.63. Karnaugh maps for D flip-flops for the counter.00 01 11 1000010 1 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1110y 1 y 0 wy2 Y 2 wy2 y 0 y 2 y 1 y 2 + + + w y 0 y 1 y 2 = 00 01 11 1000011 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1110y 1 y 0 wy2 Y 0 wy0 wy0 + = 00 01 11 1000010 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 1110y 1 y 0 wy2 Y 1 wy1 y 1 y 0 wy0 y 1 + + = Karnaugh maps for D flip-flops for the
View Full Document
Unlocking...