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# TAMU ECEN 248 - LAB 1: DIGITAL LOGIC GATES

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LAB 1: DIGITAL LOGIC GATES ECEN 248-509 – TA: Daojing Guo Harlyn Nguyen Date: February 20th, 2021.Objectives: In this lab I will learned about the 7400 series logic gates (AND2, OR2, NOT (INV), NOR2, NAND2, XOR2. Through this lab, I will have a deeper understand how these logic gate operated on the digital circuit. Design: A 5V power supply will be used to test whether the design work properly or not. Connect the power. Connect the VCC end of the logic gate to the positive (red) end of the power, and the GRD end to the negative (black) end of the power. Then connect the inputs (A and B) of the logic gate according to the true table and measured the output (Y). Truth table of NOT (INV) gate (74ALS04) Truth table of AND2 gate (74ALS08) A Y 0 1 1 0 A B Y 0 0 0 0 1 0 1 0 0 1 1 1 Truth table of OR2 gate (74ALS32) Truth table of NAND2 gate (74ALS00A) A B Y 0 0 0 0 1 1 1 0 1 1 1 1 A B Y 0 0 1 0 1 1 1 0 1 1 1 0 Truth table of NOR2 gate (74HCT02) Truth table of XOR2 gate (74ALS86) A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y 0 0 0 0 1 1 1 0 1 1 1 0Schematic for NOR (INV) gate Schematic of AND2 gate Schematic of OR2 gate Schematic of NAND2 gate Schematic of NOR2 gate Schematic of NOR2 gate Results The designed circuit for all logic gates behaved as expected. There was no need to fix the circuit at any point. However, there is only one logic gate that need to be notice, which is the NOR2 gate. The input and output of this gate are switched position on the 7400 series. Therefore, we need to pay attention to the position in order to obtain the correct result. As we see above the standard true table is operated in term of 0 and 1. And since, we use 5V to help indicated whether our design is running correct or not. Therefore, anywhere that the multimeter reading is between 4-5V, we will be considered is as high (H), which is “1” for our Input A Output Y Input A Input B Output Y Input A Input B Output Y Input A Input B Output Y Input A Input B Output Y Input A Input B Output Ytruth table. Otherwise, if the reading is 0V, then it will be low (L), which is “0” on the truth table. As the final result, we obtained the following truth tables for the logic gates. Obtained truth table for NOT(INV) gate Obtained truth table for AND2 gate A (H/L) Y (volts) Y (H/L) H 0 L L 4.816 H A (H/L) B (H/L) AND2 (V) AND2 (H/L) L L 0 L L H 0 L H L 0 L H H 4.816 H Obtained truth table for OR2 gate Obtained truth table for NAND 2 gate A (H/L) B (H/L) OR2 (V) OR2 (H/L) L L 0 L L H 4.816 H H L 4.816 H H H 4.816 H A (H/L) B (H/L) AND2 (V) AND2 (H/L) L L 4.816 H L H 4.816 H H L 4.816 H H H 0 L Obtained truth table for NOR2 gate Obtained truth table for XOR2 gate A (H/L) B (H/L) AND2 (V) AND2 (H/L) L L 4.816 H L H 0 L H L 0 L H H 0 L A (H/L) B (H/L) AND2 (V) AND2 (H/L) L L 0 L L H 4.816 H H L 4.816 H H H 0 L Conclusion Through the lab I learn how the 14 legs 7400 series operated and how to connect them on the circuit board. Additionally, I also learned some of the gate, NOR gate, connection is different from the others. Overall, most of the gates are having the same connectivity and positions such as their input, output, VCC, and GRD.Despite of the successful in the conducting the lab, there are some limitations that might affect the learning output. The main limitation is the confusion on how to connect the 5V power supply to the breadboard. Since some of us are doing the lab at home, and we do not have any specific equipment similar to the one that is in the lab setting. But there wasn’t any specific instruction on how to implement the alternative set to get the power. Therefore, to resolve this, a description on how put the power using the barrel-jack is recommended on the instruction to help the student able to deliver the power to their

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