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TAMU ECEN 248 - Part-II Xi Zhang

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ECEN 248 –Introduction to Digital Systems Design (Spring 2008) (Sections: 501, 502, 503, 507)FSM for Sequence detector (Mealy Type)Sequences of input and output signalsState diagram of an FSMState table for the FSMState-assigned table for the FSMDerivation of the logic expressions Implementation of FSMCircuit that implements the specificationCircuit that implements the specificationBreak page between Ch 8.3 and 8.5Example of the serial adderState diagram for the serial adder FSMState table for the serial adder FSMState-assigned table for the serial adder Circuit for the serial adder State diagram for the serial adder (Moore-type)State table for the Moore-type serial adderState-assigned table serial adderCircuit for the Moore-type serial adder FSMECEN 248 –Introduction to Digital Systems Design (Spring 2008)(Sections: 501, 502, 503, 507)Prof. Xi ZhangECE Dept, TAMU, 333N WERChttp://dropzone.tamu.edu/~xizhang/ECEN248FSM for Sequence detector (Mealy Type) Unlike the Moore type machine, the output depends not only the current state, but also the current input.Figure 8.22. Sequences of input and output signals.Clock cycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 Sequences of input and output signalsFigure 8.23. State diagram of an FSM that realizes the task inFigure 8.22.A w 0 = z 0 = ⁄w 1 = z 1 = ⁄B w 0 = z 0 = ⁄Reset w 1 = z 0 = ⁄State diagram of an FSM A: starting state, also the state after an input w=0 is applied. B: w=1 in immediately preceding clock cycle.Figure 8.24. State table for the FSM in Figure 8.23.Present Next state Outputz state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 State table for the FSMA w 0 = z 0 = ⁄w 1 = z 1 = ⁄B w 0 = z 0 = ⁄Reset w 1 = z 0 = ⁄Figure 8.25. State-assigned table for the FSM in Figure 8.24.Present Next state Outputstate w = 0 w = 1 w = 0 w = 1 y Y Y z z A 0 0 1 0 0 B 1 0 1 0 1 State-assigned table for the FSMPresent Next state Outputz state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1Derivation of the logic expressions  Y = D = w; z = wy;Present Next state Outputstate w = 0 w = 1 w = 0 w = 1 y Y Y z z A 0 0 1 0 0 B 1 0 1 0 1Figure 8.26. Implementation of FSM in Figure 8.25.t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0 1 0 1 0 Clock y w z (b) Timing diagramClock ResetnD Q Q w z (a) Circuit y Implementation of FSMCircuit that implements the specificationClock ResetnD Q Q w z (a) Circuit y D Q Q Z Figure 8.27. Circuit that implements the specification in Figure 8.2.Figure 8.27. Circuit that implements the specification in Figure 8.2.t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 101 0 1 0 1 0 1 0 Clock y w z (b) Timing diagram1 0 Z Circuit that implements the specificationBreak page between Ch 8.3 and 8.5Figure 8.39. Block diagram for the serial adder.Sum A B + = Shift registerShift registerAdder FSM Shift registerB A a b s Clock Example of the serial adder A = an-1 an-2 …a0 B = bn-1 bn-2 …b0 A = sn-1 sn-2 …s0 = A + BFigure 8.40. State diagram for the serial adder FSM.G 00 1 ⁄ 11 1 ⁄ 10 0 ⁄ 01 0 ⁄ H 10 1 ⁄ 01 1 ⁄ 00 0 ⁄ carry-in 0 = carry-in 1 = G:H:Reset 11 0 ⁄ ab s ⁄ ( ) State diagram for the serial adder FSMFigure 8.41. State table for the serial adder FSM.Present Next state Outputsstate ab=00 01 1011 00 01 10 11G G G G H 0 1 1 0 H G H H H 1 0 0 1 State table for the serial adder FSMG 00 1 ⁄ 11 1 ⁄ 10 0 ⁄ 01 0 ⁄ H 10 1 ⁄ 01 1 ⁄ 00 0 ⁄ carry-in 0 = carry-in 1 = G:H:Reset 11 0 ⁄ ab s ⁄ ( )Figure 8.42. State-assigned table for Figure 8.41.Present Next state Outputstate ab=00 01 1011 00 01 10 11y Y s 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 State-assigned table for the serial adder Present Next state Outputsstate ab=00 01 1011 00 01 10 11G G G G H 0 1 1 0 H G H H H 1 0 0 1Figure 8.43. Circuit for the adder FSM in Figure 8.39.FulladderabsDQQcarry-outClockResetYyCircuit for the serial adderFigure 8.44. State diagram for the Moore-type serial adder FSM.H 1 s 1 = ⁄Reset H 0 s 0 = ⁄011011110110G 1 s 1 = ⁄G 0 s 0 = ⁄01100001001011000011State diagram for the serial adder (Moore-type)Figure 8.45. State table for the Moore-type serial adder FSM.Present Nextstate Outputstate ab =00 01 1011 s G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1 State table for the Moore-type serial adderH 1 s 1 = ⁄Reset H 0 s 0 = ⁄011011110110G 1 s 1 = ⁄G 0 s 0 = ⁄01100001001011000011Figure 8.46. State-assigned table for Figure 8.45.Present Nextstate state ab=00 01 10 11Outputy 2 y 1 Y 2 Y 1 s 00 0 0 01 0 1 10 0 01 0 0 01 0 1 10 1 10 0 1 10 1 0 11 0 11 0 1 10 1 0 11 1 State-assigned table serial adderPresent Nextstate Outputstate ab =00 01 1011 s G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1Figure 8.47. Circuit for the Moore-type serial adder FSM.Fulladder a b D Q Q Carry-out Clock Reset D Q Q s Y 2 Y 1 Sum bit y 2 y 1 Circuit for the Moore-type serial adder


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TAMU ECEN 248 - Part-II Xi Zhang

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