Administrivia Finish reading Chapter 4 Exam 2 answers posted questions CMSC 411 Computer Systems Architecture Lecture 22 Multiprocessors cont Mean 60 Median 60 StdDev 12 Cache simulator project due tomorrow questions ti Course evaluations open at http www CourseEvalUM umd edu Alan Sussman als cs umd edu l d d 2 CMSC 411 22 some from Patterson Sussman others Example Snooping Protocol Write through g Invalidate Protocol 2 states per block in each cache Snooping coherence protocol is usually implemented by incorporating a finite state controller t ll in i each h node d cache h Logically think of a separate controller associated with each cache block as in uniprocessor state of a block is a p vector of states Hardware state bits associated with blocks that are in the cache other blocks can be seen as being in invalid not present state in that cache That is snooping operations or cache requests for different blocks can proceed independently Writes invalidate all other cache copies In real implementations a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion can have multiple simultaneous readers of block but write invalidates them State Tag Data meaning one operation may be initiated before another is completed even though only one cache access or one bus access is allowed at a time State Tag Data Pn P1 cache cache B Bus Mem CMSC 411 22 some from Patterson Sussman others 3 CMSC 411 22 some from Patterson Sussman others I O devices 4 The Example Is Example 2 state Protocol Coherent PrRd Processor Read PrWr Processor Write BusRd Bus Read BusWr Bus Write Format event action Memory is coherent iff 1 A read by P to location X that follows a write by P to X 1 X w no intervening writes returns written value PrRd PrWr BusWr V 2 A read by P to location X that follows a write by Q to X w no intervening writes and the read and write sufficiently separated returns written value BusWr PrRd BusRd I 3 Writes to same location are serialized PrWr BusWr writes to same location by distinct processors seen in same order by all other processors Si l Single writer it multiple reader lti l d SWMR CMSC 411 22 some from Patterson Sussman others 5 Is Example 2 state Protocol Coherent 6 CMSC 411 22 some from Patterson Sussman others Ordering Assume bus transactions and memory ops atomic and a one level cache all phases of one bus transaction complete before next one starts processor waits it for f memory operation ti to t complete l t before b f issuing i i nextt P0 R P1 R R R W R R with one level cache assume invalidations applied during bus transaction Processors only observe state of memory through reads P2 R R R R R R R R W R R Writes only observable by other processors if on bus All writes go to bus in this example protocol protocol not all others Writes serialized by order in which they appear on bus bus order invalidations applied to caches in bus order Writes establish a partial order Doesn t constrain ordering of reads though shared medium bus will order read misses too How to insert reads in this order Important since processors see writes through reads so determines whether write serialization is satisfied But read hits may happen independently and do not appear on bus or enter directly in bus order CMSC 411 22 some from Patterson Sussman others 7 any order among reads between writes is fine Writes serialized reads and writes not interchanged so coherent CMSC 411 22 some from Patterson Sussman others 8 Outline Example Write Back Snoopy Protocol Review Coherence Write Consistency Administrivia Snooping Building Blocks p g protocols p and examples p Snooping Coherence traffic and Performance on MP Directory based protocols and examples C Conclusion l i Invalidation protocol write back cache Snoops every address on bus If it has a dirty copy of requested block provides that block in response to the read request and aborts the memory access Each memory block is in one state Clean in all caches and up to date in memory Shared OR Dirty in exactly one cache Exclusive OR Not in any caches Each cache block is in one state track these Shared block can be read OR Exclusive cache has only y copy y its writeable and dirty y OR Invalid block contains no data in uniprocessor cache too Read misses cause all caches to snoop bus Writes to clean blocks are treated as misses write allocate 9 CMSC 411 22 some from Patterson Sussman others Write Back State Machine CPU Events Write Back State Machine Bus events CPU Read hit State machine for CPU requests for each cache block Invalid Non resident blocks invalid CPU R Read d Place read miss on bus State machine for bus requests for each cache block Invalid Shared read only Write miss for this block Shared read only Write miss for this block CPU Write Place Write Mi on bus Miss b Write Back Block abort memory access CPU Write Place Write Miss on Bus CPU read hit CPU write hit 10 CMSC 411 22 some from Patterson Sussman others Exclusive read write Exclusive read write CMSC 411 22 some from Patterson Sussman others 11 CMSC 411 22 some from Patterson Sussman others Read miss for this block Write W it Back B k Block abort any memory access 12 Write back State Machine III Block replacement CPU Read hit local misses to conflicting blocks Invalid CPU Write Place Write Miss on bus CPU Read Place read miss on bus CPU read miss Write back block Place read miss on bus Sh d Shared read only CPU Read miss Place read miss on bus CPU Write Place Write Miss on Bus Cache C h Block Bl k State CPU read hit CPU write hit Exclusive read write Cache State for this block Exclusive read write CPU read hit CPU write hit CPU Write Miss Write back cache block Place write miss on bus CMSC 411 22 some from Patterson Sussman others 13 Example step P1 P1 Write Write 10 10 to to A1 P1 P1 Read A1A1 Read P2 P2 Read A1 CPU Read hit Write miss for this block Shared Invalid CPU R Read d read only Place read miss on bus CPU Write Place Write Miss on bus Write miss CPU read miss CPU Read miss for this block Write back block Place read miss Wi B Write Backk Place read miss on bus CPU Write Block abort on bus Place Write Miss on Bus memory access Block Read miss Write Back State machine for CPU requests o each eac for cache block and for bus requests for each cache block Block abort memory access CPU Write Miss Write back cache block Place write miss on bus 14 CMSC 411 22 some from Patterson Sussman others Example P1 State Addr P2 Value State Addr Bus Value Action Proc