CS252 S05CMSC 411Computer Systems ArchitectureLecture 6Basic Pipelining (cont.)CMSC 411 - 6 (from Patterson)2When do MIPS exceptions occur?• IF– page fault on instruction fetch– misaligned memory access– memory protection violation• ID– undefined or illegal opcode• EX– arithmetic exception• MEM– page fault on data fetch/store– misaligned memory access– memory protection violation• WB: None!CMSC 411 - 6 (from Patterson)3Examples of exception handlingLD IF ID EX MEM WBADD IF ID EX MEM WB• Handle the MEM fault first, then restartLD IF ID EX MEM WBADD IF ID EX MEM WB• IF fault occurs first, even though LD will fault later• But for precise exceptions, must handle LD fault firstCMSC 411 - 6 (from Patterson)4How is this done?• Answer: Don't handle exceptions until the WB stage– each instruction has an associated status vector that keeps track of faults– any bit set in the status vector turns off register writes and memory writes– in WB stage, the status vector is checked and any fault is handled– So, since instructions reach WB in proper order, faults for earlier instructions are handled before faults for later instructions» Unfortunately, will need to violate this later (for instructions that don’t reach WB in proper order)CMSC 411 - 6 (from Patterson)5Commitment• When an instruction is guaranteed to complete, it is committed• Life is easier if no instruction changes the permanent machine state before it is committed• In MIPS, commitment occurs at the end of the MEM stage - that’s why register update occurs in the stage after that• Some machines muddy the state before commitment, and the exception handler must do its best to restore the state that existed before the instruction startedCMSC 411 - 6 (from Patterson)6Complications with long instructions• So far, all MIPS instructions take 5 cycles• But haven't talked yet about the floating point instructions• Take it on faith that floating point instructions are inherently slower than integer arithmetic instructions– doubters may consult Appendix H in H&P onlineCS252 S05CMSC 411 - 6 (from Patterson)7How slow is slow?• Some typical times:– latency is the number of cycles between an instruction that produces a result and one that uses it– initiation interval is the number of cycles between two instructions of the same kind (for example, two ADD.Fs)Instruction Latency InitiationALU uses 0 1Load/store 1 1ADD.F,SUB.F 3 1DIV.F 24 25CMSC 411 - 6 (from Patterson)8Examples• If have a string of instructions:– ADD– SUB – AND– OR– SLLI• then there are no delays in the pipeline, because– initiation=1 means can start one of these instructions every cycle– latency=0 means that results from one instruction will be available when the next instruction needs themCMSC 411 - 6 (from Patterson)9Examples (cont.)• Suppose have a string of instructions– ADD.F– SUB.F• Then initiation=1 means that can start SUB.F one cycle behind ADD.F• But latency=3 means that this will work right only if SUB.F doesn't need ADD.Fs results• If it does need the results, then need two instructions in between ADD.F and SUB.F to prevent bubbles in the pipelineCMSC 411 - 6 (from Patterson)10Functional units - Fig. A.31CMSC 411 - 6 (from Patterson)11Examples (cont.) - Fig. A.32MUL.D IF ID M1 M2 M3 M4 M5 M6 M7 MEM WBADD.D IF ID A1 A2 A3 A4 MEM WBL.D IF ID EX MEM WBS.D IF ID EX MEM WBItalics shows where data is neededblue where a result is availableCMSC 411 - 6 (from Patterson)12Hazards caused by long instructions• The floating point adder and multiplier are pipelined, but the divider is not - that is why the initiation interval for divide is 25– A program will run very slowly if it does too many of these!• It will also run slowly if the results of the divide are needed too soonCS252 S05CMSC 411 - 6 (from Patterson)13FP stalls from RAW hazards – Fig. A.33Inst. 1 2 3 4 5 6 7 8 9L.D F4,0(R2) IF ID EX MEM WBMUL.D F0,F4,F6 IF ID stall M1 M2 M3 M4 M5ADD.D F2,F0,F8 IF stall ID stall stall stall stallS.D F2,0(R2) stall IF stall stall stall stallInst. 10 11 12 13 14 15 16 17L.DMUL.D M6 M7 MEM WBADD.D stall stall A1 A2 A3 A4 MEM WBS.D stall stall ID EX stall stall stall MEMCMSC 411 - 6 (from Patterson)14Long instructions (cont.)• It is possible that two instructions enter the WB stage at the same timeADD.D IF ID A1 A2 A3 A4 MEM WBLD IF ID ALU MEM WBDADD IF ID ALU MEM WBDADD IF ID ALU MEM WB• A structural hazardCMSC 411 - 6 (from Patterson)15Long instructions (cont.)• Instructions can finish in the wrong order• This can cause WAW hazards• This violation of WB ordering defeats the previous strategy for precise exception handling– problem is out-of-order completionDIV.D F0, F2, F4ADD R1, R1, R2SUB.D F10, F12, F14What happens if sub faults?And then div?What about R1?1) stop fetching2) turn off writes3) let pipeline drain4) handle1) stop fetching2) turn off writes3) let pipeline drain4) handleCMSC 411 - 6 (from Patterson)16WAW structural hazard1 2 3 4 5 6 7 8 9 10 11MUL.D F0,F4,F6IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB…IF ID EX MEM WB…IF ID EX MEM WBADD.D F2,F4,F6IF ID A1 A2 A3 A4 MEM WB…IF ID EX MEM WB…IF ID EX MEM WBL.D F2,0(R2)IF ID EX MEM WBCMSC 411 - 6 (from Patterson)17Possible fixes• Give up and just do imprecise exception handling– tempting, but very annoying to users• Delay WB until all previous instructions complete– since so many instructions can be active, this is expensive - requires a lot of supporting hardware• Write, to memory, a history file of register and memory changes so can undo instructions if necessary– or keep a future file of computed results that are waiting for MEM or WBCMSC 411 - 6 (from Patterson)18Possible fixes (cont.)• Let the exception handler finish the instructions in the pipeline and then restart the pipe at the next instruction• Have the floating point units diagnose exceptions in their first or second stages, so can handle them by methods that work well for handling integer exceptionsCS252 S05CMSC 411 - 6 (from Patterson)19How to detect hazards in ID• Early detection would prevent trouble• Check for structural hazards:– will the divide unit clear in time?– will WB be possible when we need it?• Check for RAW data hazards:– will all source registers be available when needed?• Check for WAW data hazards:– Is the destination register for any ADD.D, multiply or divide instruction the same register as the