Computer Systems Architecture CMSC 411 Lecture 14 Virtual Memory 1 Ilchul Yoon iyoon cs umd edu Slides also contributed by Alan Sussman Pete Keleher Chau Wen Tseng 1 Announcements HW3 on time due October 17 11pm Project 1 has been assigned Phase 0 on time due October 19 11pm Phase 1 on time due October 28 11pm Phase 2 on time due November 7 11pm 2 VIRTUAL MEMORY 3 Virtual addressing Computers are designed so that multiple programs can be active at the same time At the time a program is compiled the compiler has to assign addresses to each data item But how can it know what memory addresses are being used by other programs Instead the compiler assigns virtual addresses and expects the loader OS to provide the means to map these into physical addresses 4 In the olden days The loader would locate an unused set of main memory addresses and load the program and data there There would be a special register called the relocation register and all addresses that the program used would be interpreted as addresses relative to the base address in that register So if the program jumped to location 54 the jump would really be to 54 contents of relocation register A similar thing perhaps with a second register would happen for data references 5 In the less olden days It became difficult to find a contiguous segment of memory big enough to hold program and data So the program was divided into pages with each page stored contiguously but different pages in any available spot either in main memory or on disk This is the virtual addressing scheme to the program memory looks like a contiguous segment but actually data is scattered in main memory and perhaps on disk 6 Memory protection Each program lives in its own virtual space called its process each in turn When the CPU is working on one process others may be partially completed or waiting for attention The CPU is time shared among the processes working on And main memory is also shared among processes 7 But we know all about this Already know that a program and data can be scattered between cache memory and main memory Now add the reality that its location in main memory is also determined in a scattered way and some pages may also be located on disk So each page has its own relocation value 8 Virtual Memory Figure B 19 9 Parameters Figure B 20 Parameter First level cache Virtual memory Block page size 16 128 bytes 4096 65 536 bytes Hit time Miss penalty access time transfer time Miss rate Address mapping 1 3 clock cycles 8 200 cc 6 160 cc 2 40 cc 0 1 10 100 200 cc 106 107 cc 8 8 106 cc 2 2 106 cc 0 00001 0 001 25 45 bit physical address to 14 20 bit cache address 32 64 bit virtual address to 25 45 bit physical address 10 Cache vs virtual memory Cache Virtual memory Cache miss handled by hardware Page faults handled by OS Cache size fixed for a particular machine Virtual memory size fixed for a particular program Fundamental unit is a block Fundamental unit is a fixed length page or a variable length segment cache fault page fault 11 Old Protection Mode Base Bound User processes need to be protected from each other Two registers base and bound test whether this virtual address belongs to this process Built in Cray 1 If not a memory protection violation exception is raised Users cannot change the base and bound registers P1 bound base P2 bound base From Sussman 12 Who can change them The operating system needs access to the base and bound registers So a process that is labeled kernel also called supervisor or executive can access any memory location and change the registers Kernel processes are accessed through system calls and a return to user mode is like a subroutine return restoring the state of the user process 13 Segmentation Basically multiple base bounds w virtual memory stack bound stack base heap bound heap base Process Each segment can be located anywhere in physical memory 14 PAGING 15 The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU D0 D31 Simple addressing method of archaic pre 1978 computers Data A0 A31 Memory D0 D31 All programs shared one address space The physical address space Machine language programs had to be aware of the machine organization No way to prevent a program from accessing any machine resource in memory 16 Solution Add a Layer of Indirection Virtual Addresses Physical Addresses A0 A31 CPU D0 D31 Data Virtual Physical Address Translation A0 A31 Main Memory D0 D31 All user programs run in an standardized virtual address space starting at zero Needs fast Address Translation hardware managed by the operating system OS to map each virtual address to physical memory Hardware supports modern OS features Memory protection Address translation Sharing 17 Paging overview Fully associative mapping because page faults are really really expensive Page is located using a page table one entry per page in the virtual address space Size is sometimes reduced by hashing to make one entry per physical page in main memory an inverted page table Since locality says that a page will be used multiple times address translation usually tests the addresses of the recently referenced pages before looking in other places So address translation information is held in the translation look aside buffer TLB 18 Paging overview cont Most machines replace the LRU page moving pages between memory and disk is so slow that it s worth doing something close to real LRU Disks are so slow that machines use write back not write through and keep a dirty bit for each page 19 Page tables encode virtual address spaces A virtual address space is divided into blocks of memory called pages Address Space Physical Virtual Address Space frame frame frame frame A machine usually supports pages of a few sizes MIPS R4000 A valid page table entry encodes physical memory frame address for the page 20 Page tables Figure B 23 21 Details of Page Table Page Table Physical Memory Space frame frame frame frame Virtual Address V page no 12 offset Page Table V Access Rights PA Page Table Base Reg index into page table virtual address table located in physical memory P page no offset 12 Physical Address Page table maps virtual page numbers to physical frames PTE Page Table Entry Virtual memory treat memory cache for disk 22 Use of Page Table another view From William Stallings 23 Two Level Page Tables Each process needs its own address space Two level Page Tables 32 bit virtual address 31 22 P1 index 21 12 11 0 Page Offset P2 index Top level
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