CS252 S05CMSC 411Computer Systems ArchitectureLecture 17Storage Systems 1CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )2Storage systems• We already know about four levels of storage:– Registers– Cache– Memory– Disk• But we've been a little vague on how these devices are interconnected• In this unit, we study– Input/output units such as disks and tapes– Buses to connect storage devices– I/O performance issues– Design of file systems (won’t talk much about this)Disk and Tape TechnologiesCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )4(Hard) Disks• What it is: – A collection of 1-20 platters (like 2-sided CD's) – Between 1 and 8 inches in diameter – 2.5 & 3.5 inch most common today– Rotating on a central spindle– With 500-2500 tracks on each surface– Divided into (maybe) 64 sectors» older disks: all tracks have the same number of sectors» current disks: outer tracks have more sectors• Larger diameter: better retrieval times• Smaller diameter: cheaper and uses less power• Disk controller provides access to 1 or more disksCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )5Disks (cont.)• Used for– file storage– slowest level of virtual memory during program executionFig 7.1 from H&P 3ed.CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )6Disks (cont.)• How information is retrieved by disk controller:– Wait for previous requests to be filledTime = queuing delay– A movable arm is positioned at the correct cylinderTime = seek time– The system waits for the correct sector to appear under the armTime = rotational latencyCS252 S05CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )7Disks (cont.)• How information is retrieved by disk controller (cont.)– Then a magnetic head senses» the sector number» the information recorded in the sector» an error correction codeand the information is transferred to a bufferTime = transfer time– The disk controller may impose some extra overheadTime = controller time• Because all of this is so expensive, disk controller might also read the next sector or two, hoping that the next information needed is located there (prefetch or read ahead)CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )8Example• Average disk access time (in millisec): average seek time + average rotational delay + transfer time +controller overheadaverage seek time5 mstransfer rate 10MB/secrotation speed 8000 RPMsector size 1024 bytescontroller overhead.5 msCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )9Example (cont.)• average seek time = 5 ms• average rotational delay =• transfer time =• controller overhead = .5 ms• Total: 5 + 3.75 + .1 + .5 = 9.35 msCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )10Speed gap between memory and diskFig. 6.1CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )11Competitors to disks• Solid state disks built from DRAMs– But needs constant power• Optical disks– CDs, DVDs, Blu-Ray• Magnetic tapes– Slower, but large capacity good for backups• Automated tape libraries– Juke box technology• Flash memory– Small, fast, low powerBusesCS252 S05CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )13Buses• We've seen buses before, especially in the discussion of Tomasulo's algorithm (CDB)• Main characteristic: Buses are shared by several data paths and therefore can be bottlenecks– CPU-memory buses: physically short, high speed, design optimized for performance– I/O buses: long, handle an unknown number of devices with unpredictable characteristicsCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )14Typical bus transaction• When a READ is issued:– Bus begins in a wait state– Address sent on bus to memory, with control information to signal a read– When data is available, the wait signal is turned off and the data is transmitted• When a WRITE is issued:– Bus begins in a wait state– Address sent on bus to memory, with control information to signal a write– Then the data is transmitted, usually with no pauseCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )15Bus options – Fig. 7.8 H&P 3ed.Option High performance Low costBus width separate address and data lines multiplex address and data linesData width wider is faster (e.g., 64 bits) narrower is cheaper (e.g., 8 bits)Transfer size multiple words have less overheadsingle-word transfer is simplerBus masters multiple (need arbitration) single (no arbitration)Split transactions? yes – separate request and reply gets higher bandwidthno – continuous connection cheaper and lower latencyClocking synchronous asynchronousCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )16Who issues READs and WRITEs?• The bus master does• If the bus is between CPU and memory, then the CPU is the bus master• If it is an I/O bus, then there might be several devices, so several bus masters, and they compete for time slices on the bus– In this case, buses are often packet switched -each device divides its message into fixed length packets, and takes turns with other devices that are transmittingCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )17Synchronous vs. asynchronous buses• Buses that are clocked (synchronous) send data and addresses at fixed times, so sender and receiver always know what to expect – Makes them fast and cheap– But restricts them to be short, because of time-lag problems• Buses that are not clocked (asynchronous) use handshaking protocols to establish contact:– Sender puts message on bus to get the attention of receiver– Receiver responds– Sender transmits data– Receiver sends acknowledgement of receiptCMSC 41 1 - 17 (so me from Patterso n, Suss man, others )18Asynchronous buses• Because of handshaking protocol,– They can be slow and expensive– But it allows them to be physically long and to serve a wide variety of devices• The handshaking protocols are standardized so that device manufacturers can connect to a variety of buses– examples include IDE, ATA, SCSI, USBCS252 S05CMSC 41 1 - 17 (so me from Patterso n, Suss man, others )19How is the I/O bus connected?• Do we connect it to – the memory bus?– or to the cache?• Typical solution from Fig. 7.15 H&P 3ed.CMSC 41 1 - 18 (so me from Patterso n, Suss man, others )20How does CPU get data from I/O bus?• Two solutions:– Some (mostly older) machines have op-codes that read or write to I/O devices– In