UMD CMSC 411 - Memory Hierarchy and Cache Design (3) - D2115940

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UMD CMSC 411 - Memory Hierarchy and Cache Design (3)

School name University of Maryland, College Park

Course Cmsc 411- Computer Systems Architecture

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1Page1MemoryHierarchyandCacheDesign(3)MainMemoryBackground• ConventionalDRAMsystemMainMemoryBackground• PerformanceMetricsofMainMemory:– Latency:Affectscachemisspenalty» AccessTime:timebetweentherequestandwhenthedesiredwordarrives» CycleTime:minimumtimebetweenrequests– Bandwidth:AffectsI/Operformance&cachemisspenalty(especiallywhenalargeblockisusedintheL2cache)MainMemoryBackground• MainMemoryusesDRAM(dynamicRAM)– Dynamicbecauseoftheneedtoberefreshedperiodically(butrequiresonly1transistor/bit)– Addressesaredividedinto2parts:» RASorRowAccessStrobe» CAS orColumnAccessStrobe• CacheusesSRAM (staticRAM)– Norefresh(butrequires6transistors/bit)– Addressnotdividedforfastaccess• Comparison– Capacity:DRAMis4-8timesthatofSRAM– Cycletime:SRAMis8-16timesfasterthanDRAM– Cost:SRAMis8-16timesmoreexpensivethanDRAM2Page2TrendsinDRAMCapacityimprovesby60%peryearRowaccesstimeimprovesby7%peryearMainMemoryOrganizations• BasicMemoryOrganization– one-wordwidebus– 4clockcyclestosendtheaddress– 24clockcyclesfortheaccesstimeperword– 4clockcyclestosendawordofdata• Example– cacheblockof4words– misspenalty=4x(4+24+4)=128cyclesFasterMemorySystem1.WiderMainMemory2.SimpleInterleavedMemory3.IndependentMemoryBanks4.AvoidingMemoryBankConflicts5.DRAM-specificInterleavingFirstTechnique:WiderMainMemory• Cachemisspenalty– two-wordwidebus» 2x(4+24+4)=64cycles– four-wordwidebus» 1x(4+24+4)=32cycles• Drawbacks– Higherbuscosts– Multiplexor– Reducedexpandability– Morefrequent“read-modify-write”sinmemorieswitherrorcorrection3Page3SecondTechnique:SimpleInterleavedMemory• MemoryconsistsofseveralDRAMChips– Eachchipiscapableofautonomousoperation• Organizememorychipsinbanksandissuememoryrequeststoallbanksatthesametime• BanksareonewordwideFourwayinterleavingMemoryInterleaving• Mappingaddressestobanksaffectsthebehaviorofthememorysystem– Optimizedforsequentialaccess• Mayspreadconsecutiveaddressestoseveralbanks– InterleavingFactor– Normallywordinterleaved» Canalsobebyteinterleaved» Dependsontheorganizationofthebank• Goal:deliverinformationfromnewbankoneachcycle– Needmorebanksthanthenumberofcyclestoaccessabank• Asmemorychipsizeincreases- usefewerchips– Constructingmultiplebanksbecomesdifficult• RestrictedExpandability– Canincreasememoryonlybydoublingit• CacheMissPenalty– 4+24+4x4=44cyclesThirdTechnique:IndependentMemoryBanks• Multipleindependentbanks– Multiplememorycontrollers– Eachbankusesseparateaddressanddatalines4Page4FourthTechnique:AvoidingMemoryBankConflicts• Problemint x[256][512];for(j=0;j<512;j=j+1)for(i=0;i<256;i=i+1)x[i][j]=2*x[i][j];– Evenwith128banksthereareconflicts,since512isamultiple of128• Softwaresolutions– loopinterchange– Resizingthearray• Hardwaresolutions– BasedontheChineseRemainderTheorem– Primenumberofbanks– banknumber=addressmodnumberofbanks– addresswithinbank=addressmodnumberofwordsinbankAvoidingMemoryBankConflicts• ExampleFifthTechnique:DRAM-SpecificInterleaving• Multiplecolumnaccesses:pagemode– DRAMbuffersarowofbitsinsidetheDRAMforcolumnaccess(e.g.,16 Kbits rowfor64 Mbits DRAM)– Allowrepeatedcolumnaccesswithoutanotherrowaccess– 64Mbit DRAM:cycletime=90ns,optimizedaccess=25ns• NewDRAMs– Example:RAMBUS» eachchipactslikeamemorysystem» usesapacket-switchedbus» issynchronoustotheCPUclock» returnsavariableamountofdata»

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